nb/intel/haswell: Move USB config API into Lynx Point
Both EHCI and xHCI USB controllers are inside the PCH (southbridge). Now that mainboard USB configuration no longer depends on pei_data.h definitions, the API declarations can be placed in southbridge code. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: Ia21991b225482b33c5bc0dc52884674d301b28ba Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
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@ -12,48 +12,6 @@ struct spd_info {
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unsigned int spd_index;
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unsigned int spd_index;
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};
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};
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#if CONFIG(INTEL_LYNXPOINT_LP)
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#define MAX_USB2_PORTS 10
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#define MAX_USB3_PORTS 4
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#else
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#define MAX_USB2_PORTS 14
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#define MAX_USB3_PORTS 6
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#endif
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/* There are 8 OC pins */
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#define USB_OC_PIN_SKIP 8
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enum usb2_port_location {
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USB_PORT_SKIP = 0,
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USB_PORT_BACK_PANEL,
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USB_PORT_FRONT_PANEL,
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USB_PORT_DOCK,
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USB_PORT_MINI_PCIE,
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USB_PORT_FLEX,
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USB_PORT_INTERNAL,
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};
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/*
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* USB port length is in MRC format: binary-coded decimal length in tenths of an inch.
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* 4.2 inches -> 0x0042
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* 12.7 inches -> 0x0127
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*/
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struct usb2_port_config {
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uint16_t length;
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bool enable;
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unsigned short oc_pin;
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enum usb2_port_location location;
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};
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struct usb3_port_config {
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bool enable;
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unsigned int oc_pin;
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};
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/* Mainboard-specific USB configuration */
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extern const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS];
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extern const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS];
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/* Mainboard callback to fill in the SPD addresses */
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/* Mainboard callback to fill in the SPD addresses */
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void mb_get_spd_map(struct spd_info *spdi);
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void mb_get_spd_map(struct spd_info *spdi);
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@ -67,6 +67,48 @@
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#ifndef __ACPI__
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#ifndef __ACPI__
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#if CONFIG(INTEL_LYNXPOINT_LP)
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#define MAX_USB2_PORTS 10
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#define MAX_USB3_PORTS 4
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#else
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#define MAX_USB2_PORTS 14
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#define MAX_USB3_PORTS 6
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#endif
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/* There are 8 OC pins */
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#define USB_OC_PIN_SKIP 8
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enum usb2_port_location {
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USB_PORT_SKIP = 0,
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USB_PORT_BACK_PANEL,
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USB_PORT_FRONT_PANEL,
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USB_PORT_DOCK,
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USB_PORT_MINI_PCIE,
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USB_PORT_FLEX,
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USB_PORT_INTERNAL,
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};
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/*
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* USB port length is in MRC format: binary-coded decimal length in tenths of an inch.
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* 4.2 inches -> 0x0042
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* 12.7 inches -> 0x0127
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*/
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struct usb2_port_config {
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uint16_t length;
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bool enable;
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unsigned short oc_pin;
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enum usb2_port_location location;
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};
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struct usb3_port_config {
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bool enable;
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unsigned int oc_pin;
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};
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/* Mainboard-specific USB configuration */
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extern const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS];
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extern const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS];
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static inline int pch_is_lp(void)
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static inline int pch_is_lp(void)
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{
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{
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return CONFIG(INTEL_LYNXPOINT_LP);
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return CONFIG(INTEL_LYNXPOINT_LP);
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