mb/google/brya/variants/crota: set up gpio
Set the GPIO configuration of crota by bernadino 14 adl-p 20220112.pdf BUG=b:219891328 Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: I164bc7a8b682eb8682f02b06708bc7c72a5c449a Reviewed-on: https://review.coreboot.org/c/coreboot/+/62854 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Terry Chen
Tim Wawrzynczak
parent
390a28057c
commit
f613ce0479
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@ -0,0 +1,5 @@
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bootblock-y += gpio.c
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romstage-y += gpio.c
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ramstage-y += gpio.c
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@ -0,0 +1,167 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <baseboard/gpio.h>
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#include <baseboard/variants.h>
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#include <commonlib/helpers.h>
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#include <soc/gpio.h>
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/* Pad configuration in ramstage */
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static const struct pad_config override_gpio_table[] = {
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/* A19 : DDSP_HPD1 ==> NC */
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PAD_NC(GPP_A19, NONE),
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/* A20 : DDSP_HPD2 ==> NC */
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PAD_NC(GPP_A20, NONE),
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/* A21 : DDPC_CTRCLK ==> NC */
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PAD_NC(GPP_A21, NONE),
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/* A22 : DDPC_CTRLDATA ==> NC */
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PAD_NC(GPP_A22, NONE),
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/* C3 : SML0CLK ==> SML0_SMBCLK */
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PAD_CFG_GPO(GPP_C3, 0, DEEP),
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/* C4 : SML0DATA ==> SML0_SMBDATA */
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PAD_CFG_GPO(GPP_C4, 0, DEEP),
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/* D3 : ISH_GP3 ==> NC */
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PAD_NC(GPP_D3, NONE),
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/* D5 : SRCCLKREQ0# ==> SSD_CLKREQ_ODL */
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PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
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/* D6 : SRCCLKREQ1# ==> EMMC_CLKREQ_ODL */
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PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
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/* D13 : ISH_UART0_RXD ==> NC */
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PAD_NC(GPP_D13, NONE),
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/* D14 : ISH_UART0_TXD ==> NC */
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PAD_NC(GPP_D14, NONE),
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/* D15 : ISH_UART0_RTS# ==> NC */
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PAD_NC(GPP_D15, NONE),
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/* D19 : I2S_MCLK1_OUT ==> NC */
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PAD_NC(GPP_D19, NONE),
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/* E3 : PROC_GP0 ==> NC */
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PAD_NC(GPP_E3, NONE),
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/* E5 : SATA_DEVSLP1 ==> NC */
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PAD_NC(GPP_E5, NONE),
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/* E7 : PROC_GP1 ==> NC */
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PAD_NC(GPP_E7, NONE),
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/* E20 : DDP2_CTRLCLK ==> NC */
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PAD_NC(GPP_E20, NONE),
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/* E21 : DDP2_CTRLDATA ==> NC */
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PAD_NC(GPP_E21, NONE),
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/* E22 : DDPA_CTRLCLK ==> NC */
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PAD_NC(GPP_E22, NONE),
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/* E23 : DDPA_CTRLDATA ==> NC */
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PAD_NC(GPP_E23, NONE),
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/* F20 : EXT_PWR_GATE# ==> NC */
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PAD_NC(GPP_F20, NONE),
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/* H21 : IMGCLKOUT2 ==> VPRO_STRAP */
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PAD_CFG_GPI(GPP_H21, NONE, DEEP),
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/* H22 : IMGCLKOUT3 ==> NC */
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PAD_NC(GPP_H22, NONE),
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/* R4 : HDA_RST# ==> DMIC_CLK0_R */
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PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3),
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/* R5 : HDA_SDI1 ==> DMIC_DATA0_R */
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PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3),
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/* R6 : I2S2_TXD ==> NC */
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PAD_NC(GPP_R6, NONE),
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/* R7 : I2S2_RXD ==> NC */
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PAD_NC(GPP_R7, NONE),
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/* S0 : SNDW0_CLK ==> I2S_SPKR_SCLK_R */
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PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4),
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/* S1 : SNDW0_DATA ==> I2S_SPKR_SFRM_R */
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PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4),
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/* S2 : SNDW1_CLK ==> I2S_PCH_TX_SPKR_RX_R */
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PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4),
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/* S3 : SNDW1_DATA ==> I2S_PCH_RX_SPKR_TX */
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PAD_CFG_NF(GPP_S3, NONE, DEEP, NF4),
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/* S4 : SNDW2_CLK ==> NC */
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PAD_NC(GPP_S4, NONE),
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/* S5 : SNDW2_DATA ==> NC */
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PAD_NC(GPP_S5, NONE),
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/* S6 : SNDW3_CLK ==> NC */
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PAD_NC(GPP_S6, NONE),
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/* S7 : SNDW3_DATA ==> NC */
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PAD_NC(GPP_S7, NONE),
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/* T2 : GPP_T2 ==> eMMC_CFG */
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PAD_CFG_GPI(GPP_T2, NONE, DEEP),
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/* GPD11: LANPHYC ==> NC */
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PAD_NC(GPD11, NONE),
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};
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/* Early pad configuration in bootblock */
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static const struct pad_config early_gpio_table[] = {
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/* A12 : SATAXPCIE1 ==> EN_PP3300_WWAN */
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PAD_CFG_GPO(GPP_A12, 1, DEEP),
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/* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
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PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
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/* B3 : PROC_GP2 ==> eMMC_PERST_L */
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PAD_CFG_GPO(GPP_B3, 0, DEEP),
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/* B4 : PROC_GP3 ==> SSD_PERST_L */
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PAD_CFG_GPO(GPP_B4, 0, DEEP),
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/* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */
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PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
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/* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */
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PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
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/*
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* D1 : ISH_GP1 ==> FP_RST_ODL
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* FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down.
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* To ensure proper power sequencing for the FPMCU device, reset signal is driven low
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* early on in bootblock, followed by enabling of power. Reset signal is deasserted
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* later on in ramstage. Since reset signal is asserted in bootblock, it results in
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* FPMCU not working after a S3 resume. This is a known issue.
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*/
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PAD_CFG_GPO(GPP_D1, 0, DEEP),
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/* D2 : ISH_GP2 ==> EN_FP_PWR */
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PAD_CFG_GPO(GPP_D2, 1, DEEP),
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/* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */
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PAD_CFG_GPO(GPP_D11, 1, DEEP),
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/* D18 : UART1_TXD ==> SD_PE_RST_L */
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PAD_CFG_GPO(GPP_D18, 0, PLTRST),
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/* E0 : SATAXPCIE0 ==> WWAN_PERST_L (updated in ramstage) */
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PAD_CFG_GPO(GPP_E0, 0, DEEP),
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/* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */
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PAD_CFG_GPI(GPP_E13, NONE, DEEP),
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/* E16 : RSVD_TP ==> WWAN_RST_L (updated in ramstage) */
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PAD_CFG_GPO(GPP_E16, 0, DEEP),
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/* E15 : RSVD_TP ==> PCH_WP_OD */
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PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
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/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
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PAD_CFG_GPI(GPP_F18, NONE, DEEP),
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/* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (updated in romstage) */
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PAD_CFG_GPO(GPP_F21, 0, DEEP),
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/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
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PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
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/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
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PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
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/* H13 : I2C7_SCL ==> EN_PP3300_SD */
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PAD_CFG_GPO(GPP_H13, 1, PLTRST),
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};
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static const struct pad_config romstage_gpio_table[] = {
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/* B4 : PROC_GP3 ==> SSD_PERST_L */
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PAD_CFG_GPO(GPP_B4, 1, DEEP),
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/* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (set here for correct power sequencing) */
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PAD_CFG_GPO(GPP_F21, 1, DEEP),
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};
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const struct pad_config *variant_gpio_override_table(size_t *num)
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{
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*num = ARRAY_SIZE(override_gpio_table);
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return override_gpio_table;
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}
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const struct pad_config *variant_early_gpio_table(size_t *num)
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{
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*num = ARRAY_SIZE(early_gpio_table);
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return early_gpio_table;
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}
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const struct pad_config *variant_romstage_gpio_table(size_t *num)
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{
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*num = ARRAY_SIZE(romstage_gpio_table);
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return romstage_gpio_table;
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}
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