Moved from freebios
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@863 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Greg Watson
parent
0322115932
commit
f655bf7f3e
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/*
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* (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Andreas Heppel <aheppel@sysgo.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* Initialisation of the PCI-to-ISA bridge and disabling the BIOS
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* write protection (for flash) in function 0 of the chip.
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* Enabling function 1 (IDE controller of the chip.
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*/
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#include <types.h>
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#include <arch/io.h>
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#include <pci.h>
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#include <printk.h>
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#include "w83c553f.h"
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#ifndef CONFIG_ISA_MEM
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#define CONFIG_ISA_MEM 0xFD000000
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#endif
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#ifndef CONFIG_ISA_IO
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#define CONFIG_ISA_IO 0xFE000000
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#endif
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#ifndef CONFIG_IDE_MAXBUS
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#define CONFIG_IDE_MAXBUS 2
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#endif
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#ifndef CONFIG_IDE_MAXDEVICE
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#define CONFIG_IDE_MAXDEVICE (CONFIG_IDE_MAXBUS*2)
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#endif
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u32 ide_bus_offset[CONFIG_IDE_MAXBUS];
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void initialise_pic(void);
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void initialise_dma(void);
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extern struct pci_ops pci_direct_ppc;
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void southbridge_early_init(void)
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{
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unsigned char reg8;
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/*
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* Set ISA memory space
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*/
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pci_direct_ppc.read_byte(0, 0x58, W83C553F_IPADCR, ®8);
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/* 16 MB ISA memory space */
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reg8 |= (W83C553F_IPADCR_IPATOM4 | W83C553F_IPADCR_IPATOM5 | W83C553F_IPADCR_IPATOM6 | W83C553F_IPADCR_IPATOM7);
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reg8 &= ~W83C553F_IPADCR_MBE512;
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pci_direct_ppc.write_byte(0, 0x58, W83C553F_IPADCR, ®8);
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}
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void southbridge_init(void)
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{
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struct pci_dev *devbusfn;
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unsigned char reg8;
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unsigned short reg16;
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unsigned int reg32;
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devbusfn = pci_find_device(W83C553F_VID, W83C553F_DID, 0);
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if (devbusfn == 0)
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{
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printk_info("Error: Cannot find W83C553F controller on any PCI bus\n");
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return;
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}
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printk_info("Found W83C553F controller\n");
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/* always enabled */
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#if 0
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pci_read_config_word(devbusfn, PCI_COMMAND, ®16);
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reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
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pci_write_config_word(devbusfn, PCI_COMMAND, reg16);
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#endif
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/*
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* Set ISA memory space
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*/
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pci_read_config_byte(devbusfn, W83C553F_IPADCR, ®8);
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/* 16 MB ISA memory space */
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reg8 |= (W83C553F_IPADCR_IPATOM4 | W83C553F_IPADCR_IPATOM5 | W83C553F_IPADCR_IPATOM6 | W83C553F_IPADCR_IPATOM7);
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reg8 &= ~W83C553F_IPADCR_MBE512;
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pci_write_config_byte(devbusfn, W83C553F_IPADCR, reg8);
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/*
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* Chip select: switch off BIOS write protection
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*/
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pci_read_config_byte(devbusfn, W83C553F_CSCR, ®8);
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reg8 |= W83C553F_CSCR_UBIOSCSE;
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reg8 &= ~W83C553F_CSCR_BIOSWP;
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pci_write_config_byte(devbusfn, W83C553F_CSCR, reg8);
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/*
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* Enable Port 92
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*/
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reg8 = W83C553F_ATSCR_P92E | W83C553F_ATSCR_KRCEE;
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pci_write_config_byte(devbusfn, W83C553F_CSCR, reg8);
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/*
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* Route IDE interrupts to IRQ 14 & 15 on 8259.
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*/
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pci_write_config_byte(devbusfn, W83C553F_IDEIRCR, 0xef);
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pci_write_config_word(devbusfn, W83C553F_PCIIRCR, 0x0000);
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/*
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* Read IDE bus offsets from function 1 device.
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* We must unmask the LSB indicating that it is an IO address.
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*/
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devbusfn = pci_find_device(W83C553F_VID, W83C553F_IDE, 0);
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if (devbusfn == 0)
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{
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printk_info("Error: Cannot find W83C553F function 1 device\n");
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return;
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}
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/*
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* Enable native mode on IDE ports and set base address.
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*/
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reg8 = W83C553F_PIR_P1NL | W83C553F_PIR_P0NL;
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pci_write_config_byte(devbusfn, W83C553F_PIR, reg8);
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pci_write_config_dword(devbusfn, PCI_BASE_ADDRESS_0, 0xffffffff);
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pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, ®32);
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pci_write_config_dword(devbusfn, PCI_BASE_ADDRESS_0, 0x1f0);
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pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, ®32);
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pci_write_config_dword(devbusfn, PCI_BASE_ADDRESS_1, 0xffffffff);
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pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, ®32);
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pci_write_config_dword(devbusfn, PCI_BASE_ADDRESS_1, 0x3f6);
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pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, ®32);
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pci_write_config_dword(devbusfn, PCI_BASE_ADDRESS_2, 0xffffffff);
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pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_2, ®32);
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pci_write_config_dword(devbusfn, PCI_BASE_ADDRESS_2, 0x170);
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pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_2, ®32);
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pci_write_config_dword(devbusfn, PCI_BASE_ADDRESS_3, 0xffffffff);
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pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_3, ®32);
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pci_write_config_dword(devbusfn, PCI_BASE_ADDRESS_3, 0x376);
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pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_3, ®32);
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/*
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* Set read-ahead duration to 0xff
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* Enable P0 and P1
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*/
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reg32 = 0x00ff0000 | W83C553F_IDECSR_P1EN | W83C553F_IDECSR_P0EN;
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pci_write_config_dword(devbusfn, W83C553F_IDECSR, reg32);
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pci_read_config_dword(devbusfn, W83C553F_IDECSR, ®32);
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pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &ide_bus_offset[0]);
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printk_debug("ide bus offset = 0x%x\n", ide_bus_offset[0]);
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ide_bus_offset[0] &= ~1;
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#if CONFIG_IDE_MAXBUS > 1
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pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_2, &ide_bus_offset[1]);
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ide_bus_offset[1] &= ~1;
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#endif
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/*
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* Enable function 1, IDE -> busmastering and IO space access
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*/
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pci_read_config_word(devbusfn, PCI_COMMAND, ®16);
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reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_IO;
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pci_write_config_word(devbusfn, PCI_COMMAND, reg16);
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pci_read_config_word(devbusfn, PCI_COMMAND, ®16);
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/*
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* Initialise ISA interrupt controller
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*/
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initialise_pic();
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/*
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* Initialise DMA controller
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*/
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initialise_dma();
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printk_info("W83C553F configuration complete\n");
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}
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void initialise_pic(void)
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{
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outb(W83C553F_PIC1_ICW1, 0x11); /* start init sequence, ICW4 needed */
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outb(W83C553F_PIC1_ICW2, 0x08); /* base address 00001 */
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outb(W83C553F_PIC1_ICW3, 0x04); /* slave on IRQ2 */
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outb(W83C553F_PIC1_ICW4, 0x01); /* x86 mode */
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outb(W83C553F_PIC1_OCW1, 0xfb); /* enable IRQ 2 */
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outb(W83C553F_PIC1_ELC, 0xf8); /* all IRQ's edge sensitive */
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outb(W83C553F_PIC2_ICW1, 0x11); /* start init sequence, ICW4 needed */
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outb(W83C553F_PIC2_ICW2, 0x08); /* base address 00001 */
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outb(W83C553F_PIC2_ICW3, 0x02); /* slave ID 2 */
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outb(W83C553F_PIC2_ICW4, 0x01); /* x86 mode */
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outb(W83C553F_PIC2_OCW1, 0xff); /* disable all IRQ's */
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outb(W83C553F_PIC2_ELC, 0xde); /* all IRQ's edge sensitive */
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outb(W83C553F_TMR1_CMOD, 0x74);
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outb(W83C553F_PIC2_OCW1, 0x20);
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outb(W83C553F_PIC1_OCW1, 0x20);
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outb(W83C553F_PIC2_OCW1, 0x2b);
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outb(W83C553F_PIC1_OCW1, 0x2b);
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}
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void initialise_dma(void)
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{
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unsigned int channel;
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unsigned int rvalue1, rvalue2;
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/* perform a H/W reset of the devices */
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outb(W83C553F_DMA1 + W83C553F_DMA1_MC, 0x00);
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outw(W83C553F_DMA2 + W83C553F_DMA2_MC, 0x0000);
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/* initialise all channels to a sane state */
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for (channel = 0; channel < 4; channel++) {
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/*
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* dependent upon the channel, setup the specifics:
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*
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* demand
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* address-increment
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* autoinitialize-disable
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* verify-transfer
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*/
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switch (channel) {
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case 0:
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rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH0SEL|W83C553F_MODE_TT_VERIFY);
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rvalue2 = (W83C553F_MODE_TM_CASCADE|W83C553F_MODE_CH0SEL);
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break;
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case 1:
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rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH1SEL|W83C553F_MODE_TT_VERIFY);
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rvalue2 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH1SEL|W83C553F_MODE_TT_VERIFY);
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break;
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case 2:
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rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH2SEL|W83C553F_MODE_TT_VERIFY);
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rvalue2 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH2SEL|W83C553F_MODE_TT_VERIFY);
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break;
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case 3:
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rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH3SEL|W83C553F_MODE_TT_VERIFY);
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rvalue2 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH3SEL|W83C553F_MODE_TT_VERIFY);
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break;
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default:
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rvalue1 = 0x00;
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rvalue2 = 0x00;
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break;
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}
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/* write to write mode registers */
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outb(W83C553F_DMA1 + W83C553F_DMA1_WM, rvalue1 & 0xFF);
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outw(W83C553F_DMA2 + W83C553F_DMA2_WM, rvalue2 & 0x00FF);
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}
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/* enable all channels */
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outb(W83C553F_DMA1 + W83C553F_DMA1_CM, 0x00);
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outw(W83C553F_DMA2 + W83C553F_DMA2_CM, 0x0000);
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/*
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* initialize the global DMA configuration
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*
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* DACK# active low
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* DREQ active high
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* fixed priority
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* channel group enable
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*/
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outb(W83C553F_DMA1 + W83C553F_DMA1_CS, 0x00);
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outw(W83C553F_DMA2 + W83C553F_DMA2_CS, 0x0000);
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}
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@ -0,0 +1,195 @@
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/*
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* (C) Copyright 2000
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* Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
|
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* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
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*
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* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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* GNU General Public License for more details.
|
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*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
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* MA 02111-1307 USA
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*/
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/* winbond access routines and defines*/
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/* from the winbond data sheet -
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The W83C553F SIO controller with PCI arbiter is a multi-function PCI device.
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Function 0 is the ISA bridge, and Function 1 is the bus master IDE controller.
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*/
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/*ISA bridge configuration space*/
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#define W83C553F_VID 0x10AD
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#define W83C553F_DID 0x0565
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#define W83C553F_IDE 0x0105
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/* Function 0 registers */
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#define W83C553F_PCICONTR 0x40 /*pci control reg*/
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#define W83C553F_SGBAR 0x41 /*scatter/gather base address reg*/
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#define W83C553F_LBCR 0x42 /*Line Buffer Control reg*/
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#define W83C553F_IDEIRCR 0x43 /*IDE Interrupt Routing Control Reg*/
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#define W83C553F_PCIIRCR 0x44 /*PCI Interrupt Routing Control Reg*/
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#define W83C553F_BTBAR 0x46 /*BIOS Timer Base Address Register*/
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#define W83C553F_IPADCR 0x48 /*ISA to PCI Address Decoder Control Register*/
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#define W83C553F_IRADCR 0x49 /*ISA ROM Address Decoder Control Register*/
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#define W83C553F_IPMHSAR 0x4a /*ISA to PCI Memory Hole STart Address Register*/
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#define W83C553F_IPMHSR 0x4b /*ISA to PCI Memory Hols Size Register*/
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#define W83C553F_CDR 0x4c /*Clock Divisor Register*/
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#define W83C553F_CSCR 0x4d /*Chip Select Control Register*/
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#define W83C553F_ATSCR 0x4e /*AT System Control register*/
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#define W83C553F_ATBCR 0x4f /*AT Bus ControL Register*/
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#define W83C553F_IRQBEE0R 0x60 /*IRQ Break Event Enable 0 Register*/
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#define W83C553F_IRQBEE1R 0x61 /*IRQ Break Event Enable 1 Register*/
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#define W83C553F_ABEER 0x62 /*Additional Break Event Enable Register*/
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#define W83C553F_DMABEER 0x63 /*DMA Break Event Enable Register*/
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/* Function 1 registers */
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#define W83C553F_PIR 0x09 /*Programming Interface Register*/
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#define W83C553F_IDECSR 0x40 /*IDE Control/Status Register*/
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/* register bit definitions */
|
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#define W83C553F_IPADCR_MBE512 0x1
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#define W83C553F_IPADCR_MBE640 0x2
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#define W83C553F_IPADCR_IPATOM4 0x10
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#define W83C553F_IPADCR_IPATOM5 0x20
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#define W83C553F_IPADCR_IPATOM6 0x40
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#define W83C553F_IPADCR_IPATOM7 0x80
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#define W83C553F_CSCR_UBIOSCSE 0x10
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#define W83C553F_CSCR_BIOSWP 0x20
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#define W83C553F_IDECSR_P0EN 0x01
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#define W83C553F_IDECSR_P0F16 0x02
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#define W83C553F_IDECSR_P1EN 0x10
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#define W83C553F_IDECSR_P1F16 0x20
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#define W83C553F_IDECSR_LEGIRQ 0x800
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#define W83C553F_ATSCR_ISARE 0x40
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#define W83C553F_ATSCR_FERRE 0x10
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#define W83C553F_ATSCR_P92E 0x04
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#define W83C553F_ATSCR_KRCEE 0x02
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#define W83C553F_ATSCR_KGA20EE 0x01
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#define W83C553F_PIR_BM 0x80
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#define W83C553F_PIR_P1PROG 0x08
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#define W83C553F_PIR_P1NL 0x04
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#define W83C553F_PIR_P0PROG 0x02
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#define W83C553F_PIR_P0NL 0x01
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/*
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* Interrupt controller
|
||||
*/
|
||||
#define W83C553F_PIC1_ICW1 CONFIG_ISA_IO + 0x20
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#define W83C553F_PIC1_ICW2 CONFIG_ISA_IO + 0x21
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#define W83C553F_PIC1_ICW3 CONFIG_ISA_IO + 0x21
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#define W83C553F_PIC1_ICW4 CONFIG_ISA_IO + 0x21
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#define W83C553F_PIC1_OCW1 CONFIG_ISA_IO + 0x21
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#define W83C553F_PIC1_OCW2 CONFIG_ISA_IO + 0x20
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#define W83C553F_PIC1_OCW3 CONFIG_ISA_IO + 0x20
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#define W83C553F_PIC1_ELC CONFIG_ISA_IO + 0x4D0
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||||
#define W83C553F_PIC2_ICW1 CONFIG_ISA_IO + 0xA0
|
||||
#define W83C553F_PIC2_ICW2 CONFIG_ISA_IO + 0xA1
|
||||
#define W83C553F_PIC2_ICW3 CONFIG_ISA_IO + 0xA1
|
||||
#define W83C553F_PIC2_ICW4 CONFIG_ISA_IO + 0xA1
|
||||
#define W83C553F_PIC2_OCW1 CONFIG_ISA_IO + 0xA1
|
||||
#define W83C553F_PIC2_OCW2 CONFIG_ISA_IO + 0xA0
|
||||
#define W83C553F_PIC2_OCW3 CONFIG_ISA_IO + 0xA0
|
||||
#define W83C553F_PIC2_ELC CONFIG_ISA_IO + 0x4D1
|
||||
|
||||
#define W83C553F_TMR1_CMOD CONFIG_ISA_IO + 0x43
|
||||
|
||||
/*
|
||||
* DMA controller
|
||||
*/
|
||||
#define W83C553F_DMA1 CONFIG_ISA_IO + 0x000 /* channel 0 - 3 */
|
||||
#define W83C553F_DMA2 CONFIG_ISA_IO + 0x0C0 /* channel 4 - 7 */
|
||||
|
||||
/* command/status register bit definitions */
|
||||
|
||||
#define W83C553F_CS_COM_DACKAL (1<<7) /* DACK# assert level */
|
||||
#define W83C553F_CS_COM_DREQSAL (1<<6) /* DREQ sense assert level */
|
||||
#define W83C553F_CS_COM_GAP (1<<4) /* group arbitration priority */
|
||||
#define W83C553F_CS_COM_CGE (1<<2) /* channel group enable */
|
||||
|
||||
#define W83C553F_CS_STAT_CH0REQ (1<<4) /* channel 0 (4) DREQ status */
|
||||
#define W83C553F_CS_STAT_CH1REQ (1<<5) /* channel 1 (5) DREQ status */
|
||||
#define W83C553F_CS_STAT_CH2REQ (1<<6) /* channel 2 (6) DREQ status */
|
||||
#define W83C553F_CS_STAT_CH3REQ (1<<7) /* channel 3 (7) DREQ status */
|
||||
|
||||
#define W83C553F_CS_STAT_CH0TC (1<<0) /* channel 0 (4) TC status */
|
||||
#define W83C553F_CS_STAT_CH1TC (1<<1) /* channel 1 (5) TC status */
|
||||
#define W83C553F_CS_STAT_CH2TC (1<<2) /* channel 2 (6) TC status */
|
||||
#define W83C553F_CS_STAT_CH3TC (1<<3) /* channel 3 (7) TC status */
|
||||
|
||||
/* mode register bit definitions */
|
||||
|
||||
#define W83C553F_MODE_TM_DEMAND (0<<6) /* transfer mode - demand */
|
||||
#define W83C553F_MODE_TM_SINGLE (1<<6) /* transfer mode - single */
|
||||
#define W83C553F_MODE_TM_BLOCK (2<<6) /* transfer mode - block */
|
||||
#define W83C553F_MODE_TM_CASCADE (3<<6) /* transfer mode - cascade */
|
||||
#define W83C553F_MODE_ADDRDEC (1<<5) /* address increment/decrement select */
|
||||
#define W83C553F_MODE_AUTOINIT (1<<4) /* autoinitialize enable */
|
||||
#define W83C553F_MODE_TT_VERIFY (0<<2) /* transfer type - verify */
|
||||
#define W83C553F_MODE_TT_WRITE (1<<2) /* transfer type - write */
|
||||
#define W83C553F_MODE_TT_READ (2<<2) /* transfer type - read */
|
||||
#define W83C553F_MODE_TT_ILLEGAL (3<<2) /* transfer type - illegal */
|
||||
#define W83C553F_MODE_CH0SEL (0<<0) /* channel 0 (4) select */
|
||||
#define W83C553F_MODE_CH1SEL (1<<0) /* channel 1 (5) select */
|
||||
#define W83C553F_MODE_CH2SEL (2<<0) /* channel 2 (6) select */
|
||||
#define W83C553F_MODE_CH3SEL (3<<0) /* channel 3 (7) select */
|
||||
|
||||
/* request register bit definitions */
|
||||
|
||||
#define W83C553F_REQ_CHSERREQ (1<<2) /* channel service request */
|
||||
#define W83C553F_REQ_CH0SEL (0<<0) /* channel 0 (4) select */
|
||||
#define W83C553F_REQ_CH1SEL (1<<0) /* channel 1 (5) select */
|
||||
#define W83C553F_REQ_CH2SEL (2<<0) /* channel 2 (6) select */
|
||||
#define W83C553F_REQ_CH3SEL (3<<0) /* channel 3 (7) select */
|
||||
|
||||
/* write single mask bit register bit definitions */
|
||||
|
||||
#define W83C553F_WSMB_CHMASKSEL (1<<2) /* channel mask select */
|
||||
#define W83C553F_WSMB_CH0SEL (0<<0) /* channel 0 (4) select */
|
||||
#define W83C553F_WSMB_CH1SEL (1<<0) /* channel 1 (5) select */
|
||||
#define W83C553F_WSMB_CH2SEL (2<<0) /* channel 2 (6) select */
|
||||
#define W83C553F_WSMB_CH3SEL (3<<0) /* channel 3 (7) select */
|
||||
|
||||
/* read/write all mask bits register bit definitions */
|
||||
|
||||
#define W83C553F_RWAMB_CH0MASK (1<<0) /* channel 0 (4) mask */
|
||||
#define W83C553F_RWAMB_CH1MASK (1<<1) /* channel 1 (5) mask */
|
||||
#define W83C553F_RWAMB_CH2MASK (1<<2) /* channel 2 (6) mask */
|
||||
#define W83C553F_RWAMB_CH3MASK (1<<3) /* channel 3 (7) mask */
|
||||
|
||||
/* typedefs */
|
||||
|
||||
#define W83C553F_DMA1_CS 0x8
|
||||
#define W83C553F_DMA1_WR 0x9
|
||||
#define W83C553F_DMA1_WSMB 0xA
|
||||
#define W83C553F_DMA1_WM 0xB
|
||||
#define W83C553F_DMA1_CBP 0xC
|
||||
#define W83C553F_DMA1_MC 0xD
|
||||
#define W83C553F_DMA1_CM 0xE
|
||||
#define W83C553F_DMA1_RWAMB 0xF
|
||||
|
||||
#define W83C553F_DMA2_CS 0xD0
|
||||
#define W83C553F_DMA2_WR 0xD2
|
||||
#define W83C553F_DMA2_WSMB 0xD4
|
||||
#define W83C553F_DMA2_WM 0xD6
|
||||
#define W83C553F_DMA2_CBP 0xD8
|
||||
#define W83C553F_DMA2_MC 0xDA
|
||||
#define W83C553F_DMA2_CM 0xDC
|
||||
#define W83C553F_DMA2_RWAMB 0xDE
|
||||
|
||||
void initialise_w83c553f(void);
|
||||
|
|
@ -0,0 +1,47 @@
|
|||
/* $Id$ */
|
||||
/* Copyright 2000 AG Electronics Ltd. */
|
||||
/* This code is distributed without warranty under the GPL v2 (see COPYING) */
|
||||
|
||||
#include <ppc.h>
|
||||
#include <ppcreg.h>
|
||||
#include <types.h>
|
||||
#include <pci.h>
|
||||
#include <arch/io.h>
|
||||
|
||||
#ifndef PNP_INDEX_REG
|
||||
#define PNP_INDEX_REG 0x15C
|
||||
#endif
|
||||
#ifndef PNP_DATA_REG
|
||||
#define PNP_DATA_REG 0x15D
|
||||
#endif
|
||||
#ifndef SIO_COM1
|
||||
#define SIO_COM1_BASE 0x3F8
|
||||
#endif
|
||||
#ifndef SIO_COM2
|
||||
#define SIO_COM2_BASE 0x2F8
|
||||
#endif
|
||||
|
||||
void pnp_output(char address, char data)
|
||||
{
|
||||
outb(address, PNP_INDEX_REG);
|
||||
outb(data, PNP_DATA_REG);
|
||||
}
|
||||
|
||||
void sio_enable(void)
|
||||
{
|
||||
/* Enable Super IO Chip */
|
||||
pnp_output(0x07, 6); /* LD 6 = UART1 */
|
||||
pnp_output(0x30, 0); /* Dectivate */
|
||||
pnp_output(0x60, SIO_COM1_BASE >> 8); /* IO Base */
|
||||
pnp_output(0x61, SIO_COM1_BASE & 0xFF); /* IO Base */
|
||||
pnp_output(0x30, 1); /* Activate */
|
||||
}
|
||||
|
||||
struct superio_control superio_NSC_pc97307_control = {
|
||||
pre_pci_init: (void *)0,
|
||||
init: (void *)0,
|
||||
finishup: (void *)0,
|
||||
defaultport: SIO_COM1_BASE,
|
||||
name: "NSC 87307"
|
||||
};
|
||||
|
||||
Loading…
Reference in New Issue