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soc/amd/picasso/fch: use [read,write]8p to avoid typecasts 

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8445f209e43366b43b9c4750bc5f074f6d4144aa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67978
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
This commit is contained in:
Felix Held 2022-09-29 16:05:41 +02:00
parent 78ba98a797
commit f69cb29c20
1 changed files with 4 additions and 4 deletions
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8
src/soc/amd/picasso/fch.c
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@ -165,12 +165,12 @@ static void al2ahb_clock_gate(void)
uint8_t al2ahb_val; uint8_t al2ahb_val;
uintptr_t al2ahb_base = ALINK_AHB_ADDRESS; uintptr_t al2ahb_base = ALINK_AHB_ADDRESS;
al2ahb_val = read8((void *)(al2ahb_base + AL2AHB_CONTROL_CLK_OFFSET)); al2ahb_val = read8p(al2ahb_base + AL2AHB_CONTROL_CLK_OFFSET);
al2ahb_val |= AL2AHB_CLK_GATE_EN; al2ahb_val |= AL2AHB_CLK_GATE_EN;
write8((void *)(al2ahb_base + AL2AHB_CONTROL_CLK_OFFSET), al2ahb_val); write8p(al2ahb_base + AL2AHB_CONTROL_CLK_OFFSET, al2ahb_val);
al2ahb_val = read8((void *)(al2ahb_base + AL2AHB_CONTROL_HCLK_OFFSET)); al2ahb_val = read8p(al2ahb_base + AL2AHB_CONTROL_HCLK_OFFSET);
al2ahb_val |= AL2AHB_HCLK_GATE_EN; al2ahb_val |= AL2AHB_HCLK_GATE_EN;
write8((void *)(al2ahb_base + AL2AHB_CONTROL_HCLK_OFFSET), al2ahb_val); write8p(al2ahb_base + AL2AHB_CONTROL_HCLK_OFFSET, al2ahb_val);
} }
/* configure the general purpose PCIe clock outputs according to the devicetree settings */ /* configure the general purpose PCIe clock outputs according to the devicetree settings */