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mb/google/hatch: Enable FP MCU 

AP communicates with FP MCU through gspi1.

BUG=b:126455006
BRANCH=None
TEST=ensure during bootup we see spi id spi-PRP0001:01 in dmesg
     FP MCU fw is not ready yet, so not much testing to be done yet.

Signed-off-by: Shelley Chen <shchen@google.com>

Change-Id: I2eba205d5e63664dca684fbd849454c5a2fe0d0e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32017
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Shelley Chen 2019-03-21 10:05:53 -07:00 committed by Patrick Georgi
parent c325fa1312
commit f71792f8c9
2 changed files with 15 additions and 2 deletions
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12
src/mainboard/google/hatch/variants/baseboard/devicetree.cb
View File

@ -25,6 +25,7 @@ chip soc/intel/cannonlake
#| | required to set up a BAR | #| | required to set up a BAR |
#| | for TPM communication | #| | for TPM communication |
#| | before memory is up | #| | before memory is up |
#| GSPI1 | FP MCU |
#| I2C0 | Touchpad | #| I2C0 | Touchpad |
#| I2C1 | Touch screen | #| I2C1 | Touch screen |
#| I2C4 | Audio | #| I2C4 | Audio |
@ -321,7 +322,16 @@ chip soc/intel/cannonlake
device spi 0 on end device spi 0 on end
end end
end # GSPI #0 end # GSPI #0
device pci 1e.3 off end # GSPI #1 device pci 1e.3 on
chip drivers/spi/acpi
register "name" = ""CRFP""
register "hid" = "ACPI_DT_NAMESPACE_HID"
register "uid" = "1"
register "compat_string" = ""google,cros-ec-spi""
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A23_IRQ)"
device spi 1 on end
end # FPMCU
end # GSPI #1
device pci 1f.0 on device pci 1f.0 on
chip ec/google/chromeec chip ec/google/chromeec
device pnp 0c09.0 on end device pnp 0c09.0 on end

5
src/mainboard/google/hatch/variants/baseboard/gpio.c
View File

@ -62,7 +62,10 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPI_SCI(GPP_A21, NONE, DEEP, EDGE_SINGLE, INVERT), PAD_CFG_GPI_SCI(GPP_A21, NONE, DEEP, EDGE_SINGLE, INVERT),
/* A22 : FPMCU_PCH_BOOT0 */ /* A22 : FPMCU_PCH_BOOT0 */
PAD_CFG_GPO(GPP_A22, 0, DEEP), PAD_CFG_GPO(GPP_A22, 0, DEEP),
/* A23 : FPMCU_PCH_INT_ODL */ /* A23 : FPMCU_PCH_INT_ODL
* TODO Configure it back to invert mode, when
* ITSS IPCx configuration is fixed in FSP.
*/
PAD_CFG_GPI_APIC(GPP_A23, NONE, PLTRST, LEVEL, NONE), PAD_CFG_GPI_APIC(GPP_A23, NONE, PLTRST, LEVEL, NONE),
/* B0 : CORE_VID0 */ /* B0 : CORE_VID0 */