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samus: Enable XHCI mode by default 

- Enable xhci_default setting in devicetree
- Enable usb_xhci_on_resume setting for PEI

Change-Id: I2a3965a222ce571a2ad43f568fc2d0ecb94a77bc
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/180673
(cherry picked from commit c5ef875f6d148964b8ad62a3fe79916c758dbc57)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6908
Tested-by: build bot (Jenkins)
This commit is contained in:
Duncan Laurie 2013-12-18 10:55:48 -08:00 committed by Isaac Christensen
parent d5acaaf845
commit f7c308edea
2 changed files with 4 additions and 0 deletions
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3
src/mainboard/google/samus/devicetree.cb
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@ -80,6 +80,9 @@ chip northbridge/intel/haswell
# Disable PCIe CLKOUT 1-5 and CLKOUT_XDP # Disable PCIe CLKOUT 1-5 and CLKOUT_XDP
register "icc_clock_disable" = "0x013e0000" register "icc_clock_disable" = "0x013e0000"
# Route all USB ports to XHCI per default
register "xhci_default" = "1"
device pci 13.0 on end # Smart Sound Audio DSP device pci 13.0 on end # Smart Sound Audio DSP
device pci 14.0 on end # USB3 XHCI device pci 14.0 on end # USB3 XHCI
device pci 15.0 on end # Serial I/O DMA device pci 15.0 on end # Serial I/O DMA

1
src/mainboard/google/samus/romstage.c
View File

@ -126,6 +126,7 @@ void mainboard_romstage_entry(unsigned long bist)
.dimm_channel0_disabled = 2, .dimm_channel0_disabled = 2,
.dimm_channel1_disabled = 2, .dimm_channel1_disabled = 2,
.max_ddr3_freq = 1600, .max_ddr3_freq = 1600,
.usb_xhci_on_resume = 1,
.usb2_ports = { .usb2_ports = {
/* Length, Enable, OCn#, Location */ /* Length, Enable, OCn#, Location */
{ 0x0080, 1, 0, /* P0: HOST PORT */ { 0x0080, 1, 0, /* P0: HOST PORT */