GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

cbfs_spi: enable CBFS access in early romstage 

Currently the CBFS mmap cannot be accessed at the beginning of romstage
because it waits until DRAM is initialized. This change first loads CBFS
into SRAM and then switches to using DRAM as the backing once it is
initialized.

BUG=chromium:210230
BRANCH=none
TEST=confirm that the cbfs can be access at the beginning and end of
romstage on different boards.

Change-Id: I9fdaef392349c27ba1c19d4cd07e8ee0ac92dddc
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ccaaba266386c7d5cc62de63bdca81a0cc7c4d83
Original-Change-Id: Idabfab99765b52069755e1d1aa61bbee39501796
Original-Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/312577
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12586
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Mary Ruthven 2015-11-13 14:05:27 -08:00 committed by Patrick Georgi
parent 857829654c
commit f82e8ab697
4 changed files with 18 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/include/memlayout.h
View File

@ -79,9 +79,11 @@
/* Use either CBFS_CACHE (unified) or both (PRERAM|POSTRAM)_CBFS_CACHE */ /* Use either CBFS_CACHE (unified) or both (PRERAM|POSTRAM)_CBFS_CACHE */
#define CBFS_CACHE(addr, size) REGION(cbfs_cache, addr, size, 4) #define CBFS_CACHE(addr, size) REGION(cbfs_cache, addr, size, 4)
/* TODO: This only works if you never access CBFS in romstage before RAM is up! #if ENV_ROMSTAGE
* If you need to change that assumption, you have some work ahead of you... */ #define PRERAM_CBFS_CACHE(addr, size) CBFS_CACHE(addr, size)
#if defined(__PRE_RAM__) && !ENV_ROMSTAGE #define POSTRAM_CBFS_CACHE(addr, size) \
REGION(dram_cbfs_cache, addr, size, 4)
#elif defined(__PRE_RAM__)
#define PRERAM_CBFS_CACHE(addr, size) CBFS_CACHE(addr, size) #define PRERAM_CBFS_CACHE(addr, size) CBFS_CACHE(addr, size)
#define POSTRAM_CBFS_CACHE(addr, size) \ #define POSTRAM_CBFS_CACHE(addr, size) \
REGION(unused_cbfs_cache, addr, size, 4) REGION(unused_cbfs_cache, addr, size, 4)

4
src/include/symbols.h
View File

@ -41,6 +41,10 @@ extern u8 _stack[];
extern u8 _estack[]; extern u8 _estack[];
#define _stack_size (_estack - _stack) #define _stack_size (_estack - _stack)
extern u8 _dram_cbfs_cache[];
extern u8 _edram_cbfs_cache[];
#define _dram_cbfs_cache_size (_edram_cbfs_cache - _dram_cbfs_cache)
extern u8 _cbfs_cache[]; extern u8 _cbfs_cache[];
extern u8 _ecbfs_cache[]; extern u8 _ecbfs_cache[];
#define _cbfs_cache_size (_ecbfs_cache - _cbfs_cache) #define _cbfs_cache_size (_ecbfs_cache - _cbfs_cache)

7
src/lib/cbfs_spi.c
View File

@ -22,6 +22,7 @@
#include <boot_device.h> #include <boot_device.h>
#include <spi_flash.h> #include <spi_flash.h>
#include <symbols.h> #include <symbols.h>
#include <cbmem.h>
static struct spi_flash *spi_flash_info; static struct spi_flash *spi_flash_info;
@ -42,6 +43,12 @@ static const struct region_device_ops spi_ops = {
static struct mmap_helper_region_device mdev = static struct mmap_helper_region_device mdev =
MMAP_HELPER_REGION_INIT(&spi_ops, 0, CONFIG_ROM_SIZE); MMAP_HELPER_REGION_INIT(&spi_ops, 0, CONFIG_ROM_SIZE);
static void initialize_mdev(int unused)
{
mmap_helper_device_init(&mdev, _dram_cbfs_cache, _dram_cbfs_cache_size);
}
ROMSTAGE_CBMEM_INIT_HOOK(initialize_mdev);
void boot_device_init(void) void boot_device_init(void)
{ {
int bus = CONFIG_BOOT_MEDIA_SPI_BUS; int bus = CONFIG_BOOT_MEDIA_SPI_BUS;

15
src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
View File

@ -38,16 +38,7 @@ SECTIONS
QCA_SHARED_RAM(2A03F000, 4K) QCA_SHARED_RAM(2A03F000, 4K)
*/ */
STACK(0x2A040000, 16K) STACK(0x2A040000, 16K)
#ifdef __PRE_RAM__ PRERAM_CBFS_CACHE(0x2A044000, 93K)
/*
* ipq8064 is different from most other ARM platforms: it loads the
* proprietary DRAM initialization code from CBFS (as opposed to compiling
* it in into rombase). As a result CBFS needs to be used before DRAM is
* availale, which means CBFS cache must be in SRAM, which in turn means
* that PRERAM_CBFS_CACHE description can not be used here.
*/
CBFS_CACHE(0x2A044000, 93K)
#endif
TTB_SUBTABLES(0x2A05B800, 2K) TTB_SUBTABLES(0x2A05B800, 2K)
TTB(0x2A05C000, 16K) TTB(0x2A05C000, 16K)
SRAM_END(0x2A060000) SRAM_END(0x2A060000)
@ -55,8 +46,6 @@ SECTIONS
DRAM_START(0x40000000) DRAM_START(0x40000000)
RAMSTAGE(0x40640000, 128K) RAMSTAGE(0x40640000, 128K)
SYMBOL(memlayout_cbmem_top, 0x59F80000) SYMBOL(memlayout_cbmem_top, 0x59F80000)
#ifndef __PRE_RAM__ POSTRAM_CBFS_CACHE(0x59F80000, 384K)
CBFS_CACHE(0x59F80000, 384K)
#endif
DMA_COHERENT(0x5A000000, 2M) DMA_COHERENT(0x5A000000, 2M)
} }