soc/intel/alderlake: Enable support for CSE stitching
This change enables support for stitching of BP1 and BP2 partitions for CSE. This currently mimics what Intel FIT tool does w.r.t. adding different components to the different partitions. BP1: * Dummy components: DLMP, IFPP, SBDT, UFSP, UFSG, OEMP. * Decomposed components from CSE FPT file: RBEP, MFTP. * Input components: PMCP, IOMP, NPHY, TBTP, PCHC. BP2: * Dummy components: DLMP, IFPP, SBDT, UFSP, UFSG, OEMP, ISHP. * Decomposed components from CSE FPT file: RBEP, FTPR, NFTP. * Input components: PMCP, IOMP, NPHY, TBTP, PCHC, IUNP. BUG=b:189177580,b:189177538 Change-Id: I2b14405aab2a4919431d9c16bc7ff2eb1abf1f6b Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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@ -321,4 +321,11 @@ config SOC_INTEL_CRASHLOG
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help
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Enables CrashLog.
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if STITCH_ME_BIN
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config CSE_BPDT_VERSION
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default "1.7"
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endif
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endif
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@ -56,4 +56,27 @@ smm-y += xhci.c
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CPPFLAGS_common += -I$(src)/soc/intel/alderlake
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CPPFLAGS_common += -I$(src)/soc/intel/alderlake/include
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ifeq ($(CONFIG_STITCH_ME_BIN),y)
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$(call cse_add_dummy_to_bp1_bp2,DLMP)
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$(call cse_add_dummy_to_bp1_bp2,IFPP)
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$(call cse_add_dummy_to_bp1_bp2,SBDT)
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$(call cse_add_decomp_to_bp1_bp2,RBEP)
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$(call cse_add_dummy_to_bp1_bp2,UFSP)
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$(call cse_add_dummy_to_bp1_bp2,UFSG)
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$(call cse_add_dummy_to_bp1_bp2,OEMP)
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$(call cse_add_input_to_bp1_bp2,PMCP)
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$(call cse_add_decomp,bp1,MFTP)
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$(call cse_add_decomp,bp2,FTPR)
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$(call cse_add_input_to_bp1_bp2,IOMP)
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$(call cse_add_input_to_bp1_bp2,NPHY)
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$(call cse_add_input_to_bp1_bp2,TBTP)
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$(call cse_add_input_to_bp1_bp2,PCHC)
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$(call cse_add_decomp,bp2,NFTP)
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$(call cse_add_dummy,bp2,ISHP)
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$(call cse_add_input,bp2,IUNP)
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endif
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endif
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