GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

kontron/986lcd-m,roda/rk886ex: Drop secondary PCI reset 

The extra PCI bus RST# and 200ms delay there was workaround
for custom add-on hardware.

Change-Id: I38c4677cfb41d620498be8e0c257b517995bad5c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Kyösti Mälkki 2019-10-02 23:29:07 +03:00
parent ad787e18e0
commit f9891c8b46
4 changed files with 0 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/mainboard/kontron/986lcd-m/romstage.c
View File

@ -245,9 +245,6 @@ void mainboard_romstage_entry(void)
enable_lapic(); enable_lapic();
/* Force PCIRST# to conventional PCI slot and Firewire. */
ich7_p2p_secondary_reset();
ich7_enable_lpc(); ich7_enable_lpc();
early_superio_config_w83627thg(); early_superio_config_w83627thg();

3
src/mainboard/roda/rk886ex/romstage.c
View File

@ -208,9 +208,6 @@ void mainboard_romstage_entry(void)
enable_lapic(); enable_lapic();
/* Force PCIRST# to cardbus add-on. */
ich7_p2p_secondary_reset();
ich7_enable_lpc(); ich7_enable_lpc();
early_superio_config(); early_superio_config();

9
src/northbridge/intel/i945/early_init.c
View File

@ -17,7 +17,6 @@
#include <cf9_reset.h> #include <cf9_reset.h>
#include <console/console.h> #include <console/console.h>
#include <arch/io.h> #include <arch/io.h>
#include <delay.h>
#include <device/pci.h> #include <device/pci.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <device/pci_def.h> #include <device/pci_def.h>
@ -869,14 +868,6 @@ static void ich7_setup_pci_express(void)
pci_write_config32(PCI_DEV(0, 0x1c, 0), 0xd8, 0x00110000); pci_write_config32(PCI_DEV(0, 0x1c, 0), 0xd8, 0x00110000);
} }
void ich7_p2p_secondary_reset(void)
{
pci_devfn_t p2p_bridge = PCI_DEV(0, 0x1e, 0);
pci_s_assert_secondary_reset(p2p_bridge);
mdelay(200);
pci_s_deassert_secondary_reset(p2p_bridge);
}
void i945_early_initialization(void) void i945_early_initialization(void)
{ {
/* Print some chipset specific information */ /* Print some chipset specific information */

2
src/southbridge/intel/i82801gx/i82801gx.h
View File

@ -39,8 +39,6 @@
void i82801gx_enable(struct device *dev); void i82801gx_enable(struct device *dev);
#endif #endif
void ich7_p2p_secondary_reset(void);
void enable_smbus(void); void enable_smbus(void);
#if ENV_ROMSTAGE #if ENV_ROMSTAGE