soc/intel/cannonlake: Use new IRQ module
Since GPIO IO-APIC IRQs are fixed in hardware (RO registers), this patch
allows cannonlake boards to dynamically assign PCI IRQs. This means not
relying on FSP defaults, which eliminates the problem of PCI IRQs
interfering with GPIO IRQs routed to the same IRQ, when both have
selected IO-APIC routing.
Also prodrive/hermes (intel/cannonlake) was the only user of
uart_acpi_write_irq(), therefore use the allocated IRQ instead of the
fixed IRQ number in that function to preserve behavior.
BUG=b:130217151
TEST=on dratini, grep 'IO-APIC' /proc/interrupts (compressed to fit)
0: 11 0 0 0 IO-APIC 2-edge timer
1: 0 661 0 0 IO-APIC 1-edge i8042
8: 0 0 0 0 IO-APIC 8-edge rtc0
9: 0 874 0 0 IO-APIC 9-fasteoi acpi
14: 0 0 1 0 IO-APIC 14-fasteoi INT34BB:00
17: 0 10633 0 0 IO-APIC 17-fasteoi mmc1
19: 0 0 0 0 IO-APIC 19-fasteoi mmc0
22: 0 0 0 0 IO-APIC 22-fasteoi i801_smbus
26: 153738 0 0 0 IO-APIC 26-fasteoi idma64.0, i2c_designwar
27: 0 8 0 0 IO-APIC 27-fasteoi idma64.1, i2c_designwar
30: 0 0 227 0 IO-APIC 30-fasteoi i2c_designware.2
33: 0 0 0 0 IO-APIC 33-fasteoi idma64.3
35: 43107 0 0 0 IO-APIC 35-fasteoi idma64.4, pxa2xx-spi.4
36: 0 0 2039 0 IO-APIC 36-fasteoi idma64.5, pxa2xx-spi.5
45: 0 0 9451 0 IO-APIC 45-edge ELAN0000:00
85: 0 0 0 0 IO-APIC 85-fasteoi chromeos-ec
93: 0 7741 0 0 IO-APIC 93-edge cr50_spi
abbreviated _PRT dump:
If (PICM)
Package () {0x0001FFFF, 0x00, 0x00, 0x10},
Package () {0x0001FFFF, 0x01, 0x00, 0x11},
Package () {0x0001FFFF, 0x02, 0x00, 0x12},
Package () {0x0002FFFF, 0x00, 0x00, 0x13},
Package () {0x0004FFFF, 0x00, 0x00, 0x14},
Package () {0x0005FFFF, 0x00, 0x00, 0x15},
Package () {0x0008FFFF, 0x00, 0x00, 0x16},
Package () {0x0012FFFF, 0x01, 0x00, 0x17},
Package () {0x0012FFFF, 0x02, 0x00, 0x10},
Package () {0x0012FFFF, 0x00, 0x00, 0x18},
Package () {0x0013FFFF, 0x00, 0x00, 0x19},
Package () {0x0014FFFF, 0x00, 0x00, 0x11}
Package () {0x0014FFFF, 0x01, 0x00, 0x12},
Package () {0x0014FFFF, 0x02, 0x00, 0x13},
Package () {0x0014FFFF, 0x03, 0x00, 0x14},
Package () {0x0015FFFF, 0x00, 0x00, 0x1A},
Package () {0x0015FFFF, 0x01, 0x00, 0x1B},
Package () {0x0015FFFF, 0x02, 0x00, 0x1C},
Package () {0x0015FFFF, 0x03, 0x00, 0x1D},
Package () {0x0016FFFF, 0x00, 0x00, 0x15},
Package () {0x0016FFFF, 0x01, 0x00, 0x16},
Package () {0x0016FFFF, 0x02, 0x00, 0x17},
Package () {0x0016FFFF, 0x03, 0x00, 0x10},
Package () {0x0017FFFF, 0x00, 0x00, 0x11},
Package () {0x0019FFFF, 0x00, 0x00, 0x1E},
Package () {0x0019FFFF, 0x01, 0x00, 0x1F},
Package () {0x0019FFFF, 0x02, 0x00, 0x20},
Package () {0x001AFFFF, 0x00, 0x00, 0x12},
Package () {0x001CFFFF, 0x00, 0x00, 0x10},
Package () {0x001CFFFF, 0x01, 0x00, 0x11},
Package () {0x001CFFFF, 0x02, 0x00, 0x12},
Package () {0x001CFFFF, 0x03, 0x00, 0x13},
Package () {0x001DFFFF, 0x00, 0x00, 0x10},
Package () {0x001DFFFF, 0x01, 0x00, 0x11},
Package () {0x001DFFFF, 0x02, 0x00, 0x12},
Package () {0x001DFFFF, 0x03, 0x00, 0x13},
Package () {0x001EFFFF, 0x00, 0x00, 0x21},
Package () {0x001EFFFF, 0x01, 0x00, 0x22},
Package () {0x001EFFFF, 0x02, 0x00, 0x23},
Package () {0x001EFFFF, 0x03, 0x00, 0x24},
Package () {0x001FFFFF, 0x01, 0x00, 0x15},
Package () {0x001FFFFF, 0x02, 0x00, 0x16},
Package () {0x001FFFFF, 0x03, 0x00, 0x17},
Package () {0x001FFFFF, 0x00, 0x00, 0x14},
Else
Package () {0x0001FFFF, 0x00, 0x00, 0x0B},
Package () {0x0001FFFF, 0x01, 0x00, 0x0A},
Package () {0x0001FFFF, 0x02, 0x00, 0x0B},
Package () {0x0002FFFF, 0x00, 0x00, 0x0B},
Package () {0x0004FFFF, 0x00, 0x00, 0x0B},
Package () {0x0005FFFF, 0x00, 0x00, 0x0B},
Package () {0x0008FFFF, 0x00, 0x00, 0x0B},
Package () {0x0012FFFF, 0x01, 0x00, 0x0B},
Package () {0x0012FFFF, 0x02, 0x00, 0x0B},
Package () {0x0014FFFF, 0x00, 0x00, 0x0A},
Package () {0x0014FFFF, 0x01, 0x00, 0x0B},
Package () {0x0014FFFF, 0x02, 0x00, 0x0B},
Package () {0x0014FFFF, 0x03, 0x00, 0x0B},
Package () {0x0016FFFF, 0x00, 0x00, 0x0B},
Package () {0x0016FFFF, 0x01, 0x00, 0x0B},
Package () {0x0016FFFF, 0x02, 0x00, 0x0B},
Package () {0x0016FFFF, 0x03, 0x00, 0x0B},
Package () {0x0017FFFF, 0x00, 0x00, 0x0A},
Package () {0x001AFFFF, 0x00, 0x00, 0x0B},
Package () {0x001CFFFF, 0x00, 0x00, 0x0B},
Package () {0x001CFFFF, 0x01, 0x00, 0x0A},
Package () {0x001CFFFF, 0x02, 0x00, 0x0B},
Package () {0x001CFFFF, 0x03, 0x00, 0x0B},
Package () {0x001DFFFF, 0x00, 0x00, 0x0B},
Package () {0x001DFFFF, 0x01, 0x00, 0x0A},
Package () {0x001DFFFF, 0x02, 0x00, 0x0B},
Package () {0x001DFFFF, 0x03, 0x00, 0x0B},
Package () {0x001FFFFF, 0x01, 0x00, 0x0B},
Package () {0x001FFFFF, 0x02, 0x00, 0x0B},
Package () {0x001FFFFF, 0x03, 0x00, 0x0B},
Package () {0x001FFFFF, 0x00, 0x00, 0x0B},
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I914ac65470635f351d6311dc9b65e8e4d8d8ecfc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55968
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Tim Wawrzynczak
parent
664c58ab95
commit
f9bb1b46a2
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@ -89,6 +89,7 @@ config CPU_SPECIFIC_OPTIONS
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select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
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select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
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select SOC_INTEL_COMMON_BLOCK_HDA
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select SOC_INTEL_COMMON_BLOCK_IRQ
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select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT
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select SOC_INTEL_COMMON_BLOCK_SA
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select SOC_INTEL_COMMON_BLOCK_SCS
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@ -1,144 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <soc/irq.h>
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Name (PICP, Package () {
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/* PCI Bridge */
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/* cAVS, SMBus, GbE, Nothpeak */
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Package(){0x001FFFFF, 0, 0, cAVS_INTA_IRQ },
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Package(){0x001FFFFF, 1, 0, SMBUS_INTB_IRQ },
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Package(){0x001FFFFF, 2, 0, GbE_INTC_IRQ },
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Package(){0x001FFFFF, 3, 0, TRACE_HUB_INTD_IRQ },
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/* SerialIo and SCS */
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Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ },
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Package(){0x001EFFFF, 1, 0, LPSS_UART1_IRQ },
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Package(){0x001EFFFF, 2, 0, LPSS_SPI0_IRQ },
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Package(){0x001EFFFF, 3, 0, LPSS_SPI1_IRQ },
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/* PCI Express Port 9-16 */
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Package(){0x001DFFFF, 0, 0, PCIE_9_IRQ },
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Package(){0x001DFFFF, 1, 0, PCIE_10_IRQ },
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Package(){0x001DFFFF, 2, 0, PCIE_11_IRQ },
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Package(){0x001DFFFF, 3, 0, PCIE_12_IRQ },
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/* PCI Express Port 1-8 */
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Package(){0x001CFFFF, 0, 0, PCIE_1_IRQ },
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Package(){0x001CFFFF, 1, 0, PCIE_2_IRQ },
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Package(){0x001CFFFF, 2, 0, PCIE_3_IRQ },
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Package(){0x001CFFFF, 3, 0, PCIE_4_IRQ },
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#if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H)
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/* PCI Express Port 17-24 */
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Package(){0x001BFFFF, 0, 0, PCIE_17_IRQ },
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Package(){0x001BFFFF, 1, 0, PCIE_18_IRQ },
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Package(){0x001BFFFF, 2, 0, PCIE_19_IRQ },
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Package(){0x001BFFFF, 3, 0, PCIE_20_IRQ },
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#endif
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/* eMMC */
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Package(){0x001AFFFF, 0, 0, eMMC_IRQ },
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/* SerialIo */
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Package(){0x0019FFFF, 0, 0, LPSS_I2C4_IRQ },
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Package(){0x0019FFFF, 1, 0, LPSS_I2C5_IRQ },
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Package(){0x0019FFFF, 2, 0, LPSS_UART2_IRQ },
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/* SATA controller */
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Package(){0x0017FFFF, 0, 0, SATA_IRQ },
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/* CSME (HECI, IDE-R, Keyboard and Text redirection */
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Package(){0x0016FFFF, 0, 0, HECI_1_IRQ },
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Package(){0x0016FFFF, 1, 0, HECI_2_IRQ },
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Package(){0x0016FFFF, 2, 0, IDER_IRQ },
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Package(){0x0016FFFF, 3, 0, KT_IRQ },
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/* SerialIo */
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Package(){0x0015FFFF, 0, 0, LPSS_I2C0_IRQ },
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Package(){0x0015FFFF, 1, 0, LPSS_I2C1_IRQ },
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Package(){0x0015FFFF, 2, 0, LPSS_I2C2_IRQ },
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Package(){0x0015FFFF, 3, 0, LPSS_I2C3_IRQ },
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/* D20: xHCI, OTG, SRAM, CNVi WiFi */
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Package(){0x0014FFFF, 0, 0, XHCI_IRQ },
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Package(){0x0014FFFF, 1, 0, OTG_IRQ },
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Package(){0x0014FFFF, 2, 0, PMC_SRAM_IRQ },
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Package(){0x0014FFFF, 3, 0, CNViWIFI_IRQ },
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/* Integrated Sensor Hub */
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Package(){0x0013FFFF, 0, 0, ISH_IRQ },
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/* Thermal */
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Package(){0x0012FFFF, 0, 0, THERMAL_IRQ },
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/* Host Bridge */
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/* Root Port D1F0 */
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Package(){0x0001FFFF, 0, 0, PEG_RP_INTA_IRQ },
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Package(){0x0001FFFF, 1, 0, PEG_RP_INTB_IRQ },
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Package(){0x0001FFFF, 2, 0, PEG_RP_INTC_IRQ },
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Package(){0x0001FFFF, 3, 0, PEG_RP_INTD_IRQ },
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/* SA IGFX Device */
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Package(){0x0002FFFF, 0, 0, IGFX_IRQ },
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/* SA Thermal Device */
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Package(){0x0004FFFF, 0, 0, SA_THERMAL_IRQ },
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/* SA IPU Device */
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Package(){0x0005FFFF, 0, 0, IPU_IRQ },
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/* SA GNA Device */
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Package(){0x0008FFFF, 0, 0, GNA_IRQ },
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})
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Name (PICN, Package () {
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/*
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* If the setting change in pch_pirq_init(), then
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* please make the same static IRQ changes here as well.
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*/
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/* D31: cAVS, SMBus, GbE, Nothpeak */
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Package () { 0x001FFFFF, 0, 0, 11 },
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Package () { 0x001FFFFF, 1, 0, 10 },
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Package () { 0x001FFFFF, 2, 0, 11 },
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Package () { 0x001FFFFF, 3, 0, 11 },
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/* D30: Can't use PIC*/
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/* D29: PCI Express Port 9-16 */
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Package () { 0x001DFFFF, 0, 0, 11 },
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Package () { 0x001DFFFF, 1, 0, 10 },
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Package () { 0x001DFFFF, 2, 0, 11 },
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Package () { 0x001DFFFF, 3, 0, 11 },
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/* D28: PCI Express Port 1-8 */
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Package () { 0x001CFFFF, 0, 0, 11 },
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Package () { 0x001CFFFF, 1, 0, 10 },
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Package () { 0x001CFFFF, 2, 0, 11 },
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Package () { 0x001CFFFF, 3, 0, 11 },
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#if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H)
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/* D27: PCI Express Port 17-24 */
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Package () { 0x001BFFFF, 0, 0, 11 },
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Package () { 0x001BFFFF, 1, 0, 10 },
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Package () { 0x001BFFFF, 2, 0, 11 },
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Package () { 0x001BFFFF, 3, 0, 11 },
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#endif
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/* D25: Can't use PIC*/
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/* D23 */
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Package () { 0x0017FFFF, 0, 0, 11 },
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/* D22: CSME (HECI, IDE-R, KT redirection */
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Package () { 0x0016FFFF, 0, 0, 11 },
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Package () { 0x0016FFFF, 1, 0, 10 },
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Package () { 0x0016FFFF, 2, 0, 11 },
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Package () { 0x0016FFFF, 3, 0, 11 },
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/* D21: Can't use PIC*/
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/* D20: xHCI, OTG, SRAM, CNVi WiFi */
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Package () { 0x0014FFFF, 0, 0, 11 },
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Package () { 0x0014FFFF, 1, 0, 10 },
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Package () { 0x0014FFFF, 2, 0, 11 },
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Package () { 0x0014FFFF, 3, 0, 11 },
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/* D19: Can't use PIC*/
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/* Thermal */
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Package () { 0x0012FFFF, 0, 0, 11 },
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/* P.E.G. Root Port D1F0 */
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Package () { 0x0001FFFF, 0, 0, 11 },
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Package () { 0x0001FFFF, 1, 0, 10 },
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Package () { 0x0001FFFF, 2, 0, 11 },
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Package () { 0x0001FFFF, 3, 0, 11 },
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/* SA IGFX Device */
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Package () { 0x0002FFFF, 0, 0, 11 },
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/* SA Thermal Device */
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Package () { 0x0004FFFF, 0, 0, 11 },
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/* SA IPU Device */
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Package () { 0x0005FFFF, 0, 0, 11 },
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/* SA GNA Device */
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Package () { 0x0008FFFF, 0, 0, 11 },
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})
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Method (_PRT)
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{
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If (PICM) {
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Return (^PICP)
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} Else {
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Return (^PICN)
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}
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}
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@ -1,8 +1,5 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/* PCI IRQ assignment */
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#include "pci_irqs.asl"
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/* PCR access */
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#include <soc/intel/common/acpi/pcr.asl>
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@ -7,6 +7,7 @@
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#include <intelblocks/acpi.h>
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#include <intelblocks/cfg.h>
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#include <intelblocks/gpio.h>
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#include <intelblocks/irq.h>
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#include <intelblocks/itss.h>
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#include <intelblocks/pcie_rp.h>
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#include <intelblocks/xdci.h>
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@ -156,6 +157,19 @@ void soc_init_pre_device(void *chip_info)
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pcie_rp_update_devicetree(pch_lp_rp_groups);
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}
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static void cpu_fill_ssdt(const struct device *dev)
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{
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generate_cpu_entries(dev);
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if (!generate_pin_irq_map())
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printk(BIOS_ERR, "ERROR: Failed to generate ACPI _PRT table!\n");
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}
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static void cpu_set_north_irqs(struct device *dev)
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{
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irq_program_non_pch();
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}
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static struct device_operations pci_domain_ops = {
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.read_resources = &pci_domain_read_resources,
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.set_resources = &pci_domain_set_resources,
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@ -168,7 +182,8 @@ static struct device_operations pci_domain_ops = {
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static struct device_operations cpu_bus_ops = {
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.read_resources = noop_read_resources,
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.set_resources = noop_set_resources,
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.acpi_fill_ssdt = generate_cpu_entries,
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.enable_resources = cpu_set_north_irqs,
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.acpi_fill_ssdt = cpu_fill_ssdt,
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};
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static void soc_enable(struct device *dev)
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@ -7,6 +7,7 @@
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#include <device/pci.h>
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#include <fsp/api.h>
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#include <fsp/util.h>
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#include <intelblocks/irq.h>
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#include <intelblocks/lpss.h>
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#include <intelblocks/power_limit.h>
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#include <intelblocks/pmclib.h>
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@ -34,6 +35,163 @@ static const pci_devfn_t serial_io_dev[] = {
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PCH_DEVFN_UART2
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};
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static const struct slot_irq_constraints irq_constraints[] = {
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{
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.slot = SA_DEV_SLOT_PEG,
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.fns = {
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FIXED_INT_PIRQ(SA_DEVFN_PEG0, PCI_INT_A, PIRQ_A),
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FIXED_INT_PIRQ(SA_DEVFN_PEG1, PCI_INT_B, PIRQ_B),
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FIXED_INT_PIRQ(SA_DEVFN_PEG2, PCI_INT_C, PIRQ_C),
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},
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},
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{
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.slot = SA_DEV_SLOT_IGD,
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.fns = {
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ANY_PIRQ(SA_DEVFN_IGD),
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},
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},
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{
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.slot = SA_DEV_SLOT_DSP,
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.fns = {
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ANY_PIRQ(SA_DEVFN_DSP),
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},
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},
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{
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.slot = SA_DEV_SLOT_IPU,
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.fns = {
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ANY_PIRQ(SA_DEVFN_IPU),
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},
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},
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{
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.slot = SA_DEV_SLOT_GNA,
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.fns = {
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ANY_PIRQ(SA_DEVFN_GNA),
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},
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},
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{
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.slot = PCH_DEV_SLOT_THERMAL,
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.fns = {
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ANY_PIRQ(PCH_DEVFN_THERMAL),
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ANY_PIRQ(PCH_DEVFN_UFS),
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DIRECT_IRQ(PCH_DEVFN_GSPI2),
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},
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},
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{
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.slot = PCH_DEV_SLOT_ISH,
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.fns = {
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DIRECT_IRQ(PCH_DEVFN_ISH),
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},
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},
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{
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.slot = PCH_DEV_SLOT_XHCI,
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.fns = {
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ANY_PIRQ(PCH_DEVFN_XHCI),
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ANY_PIRQ(PCH_DEVFN_USBOTG),
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ANY_PIRQ(PCH_DEVFN_CNViWIFI),
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ANY_PIRQ(PCH_DEVFN_SDCARD),
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},
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},
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{
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.slot = PCH_DEV_SLOT_SIO1,
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.fns = {
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DIRECT_IRQ(PCH_DEVFN_I2C0),
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DIRECT_IRQ(PCH_DEVFN_I2C1),
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DIRECT_IRQ(PCH_DEVFN_I2C2),
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DIRECT_IRQ(PCH_DEVFN_I2C3),
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},
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},
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{
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.slot = PCH_DEV_SLOT_CSE,
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.fns = {
|
||||
ANY_PIRQ(PCH_DEVFN_CSE),
|
||||
ANY_PIRQ(PCH_DEVFN_CSE_2),
|
||||
ANY_PIRQ(PCH_DEVFN_CSE_IDER),
|
||||
ANY_PIRQ(PCH_DEVFN_CSE_KT),
|
||||
ANY_PIRQ(PCH_DEVFN_CSE_3),
|
||||
ANY_PIRQ(PCH_DEVFN_CSE_4),
|
||||
},
|
||||
},
|
||||
{
|
||||
.slot = PCH_DEV_SLOT_SATA,
|
||||
.fns = {
|
||||
ANY_PIRQ(PCH_DEVFN_SATA),
|
||||
},
|
||||
},
|
||||
{
|
||||
.slot = PCH_DEV_SLOT_SIO2,
|
||||
.fns = {
|
||||
DIRECT_IRQ(PCH_DEVFN_I2C4),
|
||||
DIRECT_IRQ(PCH_DEVFN_I2C5),
|
||||
DIRECT_IRQ(PCH_DEVFN_UART2),
|
||||
},
|
||||
},
|
||||
{
|
||||
.slot = PCH_DEV_SLOT_STORAGE,
|
||||
.fns = {
|
||||
ANY_PIRQ(PCH_DEVFN_EMMC),
|
||||
},
|
||||
},
|
||||
#if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H)
|
||||
{
|
||||
.slot = PCH_DEV_SLOT_PCIE_2,
|
||||
.fns = {
|
||||
FIXED_INT_PIRQ(PCH_DEVFN_PCIE17, PCI_INT_A, PIRQ_A),
|
||||
FIXED_INT_PIRQ(PCH_DEVFN_PCIE18, PCI_INT_B, PIRQ_B),
|
||||
FIXED_INT_PIRQ(PCH_DEVFN_PCIE19, PCI_INT_C, PIRQ_C),
|
||||
FIXED_INT_PIRQ(PCH_DEVFN_PCIE20, PCI_INT_D, PIRQ_D),
|
||||
FIXED_INT_PIRQ(PCH_DEVFN_PCIE21, PCI_INT_A, PIRQ_A),
|
||||
FIXED_INT_PIRQ(PCH_DEVFN_PCIE22, PCI_INT_B, PIRQ_B),
|
||||
FIXED_INT_PIRQ(PCH_DEVFN_PCIE23, PCI_INT_C, PIRQ_C),
|
||||
FIXED_INT_PIRQ(PCH_DEVFN_PCIE24, PCI_INT_D, PIRQ_D),
|
||||
},
|
||||
},
|
||||
#endif
|
||||
{
|
||||
.slot = PCH_DEV_SLOT_PCIE,
|
||||
.fns = {
|
||||
FIXED_INT_PIRQ(PCH_DEVFN_PCIE1, PCI_INT_A, PIRQ_A),
|
||||
FIXED_INT_PIRQ(PCH_DEVFN_PCIE2, PCI_INT_B, PIRQ_B),
|
||||
FIXED_INT_PIRQ(PCH_DEVFN_PCIE3, PCI_INT_C, PIRQ_C),
|
||||
FIXED_INT_PIRQ(PCH_DEVFN_PCIE4, PCI_INT_D, PIRQ_D),
|
||||
FIXED_INT_PIRQ(PCH_DEVFN_PCIE5, PCI_INT_A, PIRQ_A),
|
||||
FIXED_INT_PIRQ(PCH_DEVFN_PCIE6, PCI_INT_B, PIRQ_B),
|
||||
FIXED_INT_PIRQ(PCH_DEVFN_PCIE7, PCI_INT_C, PIRQ_C),
|
||||
FIXED_INT_PIRQ(PCH_DEVFN_PCIE8, PCI_INT_D, PIRQ_D),
|
||||
},
|
||||
},
|
||||
{
|
||||
.slot = PCH_DEV_SLOT_PCIE_1,
|
||||
.fns = {
|
||||
FIXED_INT_PIRQ(PCH_DEVFN_PCIE9, PCI_INT_A, PIRQ_A),
|
||||
FIXED_INT_PIRQ(PCH_DEVFN_PCIE10, PCI_INT_B, PIRQ_B),
|
||||
FIXED_INT_PIRQ(PCH_DEVFN_PCIE11, PCI_INT_C, PIRQ_C),
|
||||
FIXED_INT_PIRQ(PCH_DEVFN_PCIE12, PCI_INT_D, PIRQ_D),
|
||||
FIXED_INT_PIRQ(PCH_DEVFN_PCIE13, PCI_INT_A, PIRQ_A),
|
||||
FIXED_INT_PIRQ(PCH_DEVFN_PCIE14, PCI_INT_B, PIRQ_B),
|
||||
FIXED_INT_PIRQ(PCH_DEVFN_PCIE15, PCI_INT_C, PIRQ_C),
|
||||
FIXED_INT_PIRQ(PCH_DEVFN_PCIE16, PCI_INT_D, PIRQ_D),
|
||||
},
|
||||
},
|
||||
{
|
||||
.slot = PCH_DEV_SLOT_SIO3,
|
||||
.fns = {
|
||||
DIRECT_IRQ(PCH_DEVFN_UART0),
|
||||
DIRECT_IRQ(PCH_DEVFN_UART1),
|
||||
DIRECT_IRQ(PCH_DEVFN_GSPI0),
|
||||
DIRECT_IRQ(PCH_DEVFN_GSPI1),
|
||||
},
|
||||
},
|
||||
{
|
||||
.slot = PCH_DEV_SLOT_LPC,
|
||||
.fns = {
|
||||
ANY_PIRQ(PCH_DEVFN_HDA),
|
||||
ANY_PIRQ(PCH_DEVFN_SMBUS),
|
||||
ANY_PIRQ(PCH_DEVFN_GBE),
|
||||
FIXED_INT_ANY_PIRQ(PCH_DEVFN_TRACEHUB, PCI_INT_A)
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/*
|
||||
* Given an enum for PCH_SERIAL_IO_MODE, 1 needs to be subtracted to get the FSP
|
||||
* UPD expected value for Serial IO since valid enum index starts from 1.
|
||||
|
|
@ -115,6 +273,46 @@ static void configure_gspi_cs(int idx, const config_t *config,
|
|||
}
|
||||
}
|
||||
|
||||
static const SI_PCH_DEVICE_INTERRUPT_CONFIG *pci_irq_to_fsp(size_t *out_count)
|
||||
{
|
||||
const struct pci_irq_entry *entry = get_cached_pci_irqs();
|
||||
SI_PCH_DEVICE_INTERRUPT_CONFIG *config;
|
||||
size_t pch_total = 0;
|
||||
size_t cfg_count = 0;
|
||||
|
||||
if (!entry)
|
||||
return NULL;
|
||||
|
||||
/* Count PCH devices */
|
||||
while (entry) {
|
||||
if (PCI_SLOT(entry->devfn) >= MIN_PCH_SLOT)
|
||||
++pch_total;
|
||||
entry = entry->next;
|
||||
}
|
||||
|
||||
/* Convert PCH device entries to FSP format */
|
||||
config = calloc(pch_total, sizeof(*config));
|
||||
entry = get_cached_pci_irqs();
|
||||
while (entry) {
|
||||
if (PCI_SLOT(entry->devfn) < MIN_PCH_SLOT) {
|
||||
entry = entry->next;
|
||||
continue;
|
||||
}
|
||||
|
||||
config[cfg_count].Device = PCI_SLOT(entry->devfn);
|
||||
config[cfg_count].Function = PCI_FUNC(entry->devfn);
|
||||
config[cfg_count].IntX = (SI_PCH_INT_PIN)entry->pin;
|
||||
config[cfg_count].Irq = entry->irq;
|
||||
++cfg_count;
|
||||
|
||||
entry = entry->next;
|
||||
}
|
||||
|
||||
*out_count = cfg_count;
|
||||
|
||||
return config;
|
||||
}
|
||||
|
||||
/* UPD parameters to be initialized before SiliconInit */
|
||||
void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
|
||||
{
|
||||
|
|
@ -527,6 +725,16 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
|
|||
|
||||
params->SiSsidTablePtr = (uintptr_t)ssid_table;
|
||||
params->SiNumberOfSsidTableEntry = ARRAY_SIZE(ssid_table);
|
||||
|
||||
/* Assign PCI IRQs */
|
||||
if (!assign_pci_irqs(irq_constraints, ARRAY_SIZE(irq_constraints)))
|
||||
die("ERROR: Unable to assign PCI IRQs, and no ACPI _PRT table is defined\n");
|
||||
|
||||
size_t pch_count = 0;
|
||||
const SI_PCH_DEVICE_INTERRUPT_CONFIG *upd_irqs = pci_irq_to_fsp(&pch_count);
|
||||
params->DevIntConfigPtr = (UINT32)((uintptr_t)upd_irqs);
|
||||
params->NumOfDevIntConfig = pch_count;
|
||||
printk(BIOS_INFO, "IRQ: Using dynamically assigned PCI IO-APIC IRQs\n");
|
||||
}
|
||||
|
||||
/* Mainboard GPIO Configuration */
|
||||
|
|
|
|||
|
|
@ -9,93 +9,4 @@
|
|||
#define PCH_IRQ10 10
|
||||
#define PCH_IRQ11 11
|
||||
|
||||
#define SCI_IRQ9 9
|
||||
#define SCI_IRQ10 10
|
||||
#define SCI_IRQ11 11
|
||||
#define SCI_IRQ20 20
|
||||
#define SCI_IRQ21 21
|
||||
#define SCI_IRQ22 22
|
||||
#define SCI_IRQ23 23
|
||||
|
||||
#define TCO_IRQ9 9
|
||||
#define TCO_IRQ10 10
|
||||
#define TCO_IRQ11 11
|
||||
#define TCO_IRQ20 20
|
||||
#define TCO_IRQ21 21
|
||||
#define TCO_IRQ22 22
|
||||
#define TCO_IRQ23 23
|
||||
|
||||
#define LPSS_I2C0_IRQ 16
|
||||
#define LPSS_I2C1_IRQ 17
|
||||
#define LPSS_I2C2_IRQ 18
|
||||
#define LPSS_I2C3_IRQ 19
|
||||
#define LPSS_I2C4_IRQ 32
|
||||
#define LPSS_I2C5_IRQ 33
|
||||
#define LPSS_SPI0_IRQ 22
|
||||
#define LPSS_SPI1_IRQ 23
|
||||
#define LPSS_SPI2_IRQ 24
|
||||
#define LPSS_UART0_IRQ 20
|
||||
#define LPSS_UART1_IRQ 21
|
||||
#define LPSS_UART2_IRQ 34
|
||||
#define SDIO_IRQ 22
|
||||
|
||||
#define cAVS_INTA_IRQ 16
|
||||
#define SMBUS_INTA_IRQ 16
|
||||
#define SMBUS_INTB_IRQ 17
|
||||
#define GbE_INTA_IRQ 16
|
||||
#define GbE_INTC_IRQ 18
|
||||
#define TRACE_HUB_INTA_IRQ 16
|
||||
#define TRACE_HUB_INTD_IRQ 19
|
||||
|
||||
#define eMMC_IRQ 16
|
||||
#define SD_IRQ 19
|
||||
|
||||
#define PCIE_1_IRQ 16
|
||||
#define PCIE_2_IRQ 17
|
||||
#define PCIE_3_IRQ 18
|
||||
#define PCIE_4_IRQ 19
|
||||
#define PCIE_5_IRQ 16
|
||||
#define PCIE_6_IRQ 17
|
||||
#define PCIE_7_IRQ 18
|
||||
#define PCIE_8_IRQ 19
|
||||
#define PCIE_9_IRQ 16
|
||||
#define PCIE_10_IRQ 17
|
||||
#define PCIE_11_IRQ 18
|
||||
#define PCIE_12_IRQ 19
|
||||
#define PCIE_14_IRQ 16
|
||||
#define PCIE_15_IRQ 17
|
||||
#define PCIE_16_IRQ 18
|
||||
#define PCIE_17_IRQ 19
|
||||
#define PCIE_18_IRQ 16
|
||||
#define PCIE_19_IRQ 17
|
||||
#define PCIE_20_IRQ 18
|
||||
#define PCIE_21_IRQ 19
|
||||
|
||||
#define SATA_IRQ 16
|
||||
|
||||
#define HECI_1_IRQ 16
|
||||
#define HECI_2_IRQ 17
|
||||
#define IDER_IRQ 18
|
||||
#define KT_IRQ 19
|
||||
#define HECI_3_IRQ 16
|
||||
|
||||
#define XHCI_IRQ 16
|
||||
#define OTG_IRQ 17
|
||||
#define PMC_SRAM_IRQ 18
|
||||
#define THERMAL_IRQ 16
|
||||
#define CNViWIFI_IRQ 19
|
||||
#define UFS_IRQ 16
|
||||
#define CIO_INTA_IRQ 16
|
||||
#define CIO_INTD_IRQ 19
|
||||
#define ISH_IRQ 20
|
||||
|
||||
#define PEG_RP_INTA_IRQ 16
|
||||
#define PEG_RP_INTB_IRQ 17
|
||||
#define PEG_RP_INTC_IRQ 18
|
||||
#define PEG_RP_INTD_IRQ 19
|
||||
|
||||
#define IGFX_IRQ 16
|
||||
#define SA_THERMAL_IRQ 16
|
||||
#define IPU_IRQ 16
|
||||
#define GNA_IRQ 16
|
||||
#endif /* _SOC_IRQ_H_ */
|
||||
|
|
|
|||
|
|
@ -47,6 +47,7 @@
|
|||
#define SA_DEV_GNA PCI_DEV(0, SA_DEV_SLOT_GNA, 0)
|
||||
|
||||
/* PCH Devices */
|
||||
#define MIN_PCH_SLOT PCH_DEV_SLOT_THERMAL
|
||||
#define PCH_DEV_SLOT_THERMAL 0x12
|
||||
#define PCH_DEVFN_THERMAL _PCH_DEVFN(THERMAL, 0)
|
||||
#define PCH_DEVFN_UFS _PCH_DEVFN(THERMAL, 5)
|
||||
|
|
|
|||
|
|
@ -9,11 +9,11 @@
|
|||
#include <device/pci_def.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <intelblocks/irq.h>
|
||||
#include <intelblocks/lpss.h>
|
||||
#include <intelblocks/uart.h>
|
||||
#include <soc/pci_devs.h>
|
||||
#include <soc/iomap.h>
|
||||
#include <soc/irq.h>
|
||||
#include <soc/nvs.h>
|
||||
#include "chip.h"
|
||||
|
||||
|
|
@ -203,23 +203,13 @@ static void uart_common_enable_resources(struct device *dev)
|
|||
|
||||
static void uart_acpi_write_irq(const struct device *dev)
|
||||
{
|
||||
struct acpi_irq irq;
|
||||
|
||||
switch (dev->path.pci.devfn) {
|
||||
case PCH_DEVFN_UART0:
|
||||
irq = (struct acpi_irq)ACPI_IRQ_LEVEL_LOW(LPSS_UART0_IRQ);
|
||||
break;
|
||||
case PCH_DEVFN_UART1:
|
||||
irq = (struct acpi_irq)ACPI_IRQ_LEVEL_LOW(LPSS_UART1_IRQ);
|
||||
break;
|
||||
case PCH_DEVFN_UART2:
|
||||
irq = (struct acpi_irq)ACPI_IRQ_LEVEL_LOW(LPSS_UART2_IRQ);
|
||||
break;
|
||||
default:
|
||||
return;
|
||||
if (CONFIG(SOC_INTEL_COMMON_BLOCK_IRQ)) {
|
||||
const int irq = get_pci_devfn_irq(dev->path.pci.devfn);
|
||||
if (irq != INVALID_IRQ) {
|
||||
struct acpi_irq airq = (struct acpi_irq)ACPI_IRQ_LEVEL_LOW(irq);
|
||||
acpi_device_write_interrupt(&airq);
|
||||
}
|
||||
}
|
||||
|
||||
acpi_device_write_interrupt(&irq);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
|
|||
Loading…
Reference in New Issue