nb/intel: Use get_int_option()

Change-Id: I8896531d6df729709456bc6e79e02136d9ea7b3b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This commit is contained in:
Angel Pons 2020-11-02 22:21:54 +01:00 committed by Patrick Georgi
parent 9dc1c51db4
commit f9c939029b
7 changed files with 11 additions and 23 deletions

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@ -116,11 +116,11 @@ void igd_compute_ggc(sysinfo_t *const sysinfo)
sysinfo->ggc = 0x0002;
else {
/* 4 for 32MB, default if not set in CMOS */
u8 gfxsize = 4;
u8 gfxsize = get_int_option("gfx_uma_size", 4);
/* Graphics Stolen Memory: 2MB GTT (0x0300) when VT-d disabled,
2MB GTT + 2MB shadow GTT (0x0b00) else. */
get_option(&gfxsize, "gfx_uma_size");
/* Handle invalid CMOS settings */
/* Only allow settings between 32MB and 352MB */
gfxsize = MIN(MAX(gfxsize, 4), 12);

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@ -149,8 +149,7 @@ static void i945_setup_bars(void)
pci_write_config32(HOST_BRIDGE, X60BAR, DEFAULT_X60BAR | 1);
/* vram size from CMOS option */
if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS)
gfxsize = 2; /* 2 for 8MB */
gfxsize = get_int_option("gfx_uma_size", 2); /* 2 for 8MB */
/* make sure no invalid setting is used */
if (gfxsize > 6)
gfxsize = 2;

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@ -707,15 +707,10 @@ static void gma_func0_disable(struct device *dev)
static void gma_func1_init(struct device *dev)
{
u8 val;
if (!CONFIG(NO_GFX_INIT))
pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
if (get_option(&val, "tft_brightness") == CB_SUCCESS)
pci_write_config8(dev, 0xf4, val);
else
pci_write_config8(dev, 0xf4, 0xff);
pci_write_config8(dev, 0xf4, get_int_option("tft_brightness", 0xff));
}
static void gma_generate_ssdt(const struct device *device)

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@ -3102,10 +3102,7 @@ void chipset_init(const int s3resume)
mchbar_write16(0x1170, 0xb880);
mchbar_clrsetbits8(0x1210, ~0, 0x84);
if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS) {
/* 0 for 32MB */
gfxsize = 0;
}
gfxsize = get_int_option("gfx_uma_size", 0); /* 0 for 32MB */
ggc = 0xb00 | ((gfxsize + 5) << 4);

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@ -25,8 +25,7 @@ static void early_graphics_setup(void)
pci_write_config8(HOST_BRIDGE, DEVEN, BOARD_DEVEN);
/* Fetch VRAM size from CMOS option */
if (get_option(&reg8, "gfx_uma_size") != CB_SUCCESS)
reg8 = 0; /* 0 for 8MB */
reg8 = get_int_option("gfx_uma_size", 0); /* 0 for 8MB */
/* Ensure the setting is valid */
if (reg8 > 6)

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@ -86,10 +86,9 @@ static void sandybridge_setup_graphics(void)
printk(BIOS_DEBUG, "Initializing Graphics...\n");
if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS) {
/* Setup IGD memory by setting GGC[7:3] = 1 for 32MB */
gfxsize = 0;
}
/* Fall back to 32 MiB for IGD memory by setting GGC[7:3] = 1 */
gfxsize = get_int_option("gfx_uma_size", 0);
reg16 = pci_read_config16(HOST_BRIDGE, GGC);
reg16 &= ~0x00f8;
reg16 |= (gfxsize + 1) << 3;

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@ -38,9 +38,8 @@ void x4x_early_init(void)
/* Enable internal GFX */
pci_write_config32(HOST_BRIDGE, D0F0_DEVEN, BOARD_DEVEN);
/* Set preallocated IGD size from CMOS */
u8 gfxsize = 6; /* 6 for 64MiB, default if not set in CMOS */
get_option(&gfxsize, "gfx_uma_size");
/* Set preallocated IGD size from CMOS, or default to 64 MiB */
u8 gfxsize = get_int_option("gfx_uma_size", 6);
if (gfxsize > 12)
gfxsize = 6;
/* Need at least 4M for cbmem_top alignment */