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mb/google/rex/var/karis: Add SOC_TCHSCR_INT settings to gpio table 

Karis use I2C touchscreen only, add SOC_TCHSCR_INT(GPP_C07) to ramstage
gpio table.

BUG=b:294155897
TEST=emerge-rex coreboot

Change-Id: Ie715cfbe1984dbe38cd933312304b42ce9088806
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit is contained in:
Tyler Wang 2023-08-24 11:16:29 +08:00 committed by Subrata Banik
parent 33a5722bd7
commit fa17a9d03c
1 changed files with 2 additions and 0 deletions
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2
src/mainboard/google/rex/variants/karis/gpio.c
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@ -109,6 +109,8 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPO(GPP_C05, 1, PLTRST), PAD_CFG_GPO(GPP_C05, 1, PLTRST),
/* GPP_C06 : [] ==> SOC_TCHSCR_RPT_EN */ /* GPP_C06 : [] ==> SOC_TCHSCR_RPT_EN */
PAD_CFG_GPO(GPP_C06, 0, DEEP), PAD_CFG_GPO(GPP_C06, 0, DEEP),
/* GPP_C07 : [] ==> SOC_TCHSCR_INT */
PAD_CFG_GPI_APIC(GPP_C07, NONE, PLTRST, LEVEL, NONE),
/* GPP_C08 : [] ==> SOCHOT_ODL */ /* GPP_C08 : [] ==> SOCHOT_ODL */
PAD_CFG_NF(GPP_C08, NONE, DEEP, NF2), PAD_CFG_NF(GPP_C08, NONE, DEEP, NF2),
/* GPP_C09 : net NC is not present in the given design */ /* GPP_C09 : net NC is not present in the given design */