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mediatek/mt8173: Provide I2C bus initialization API 

BRANCH=none
BUG=none
TEST=build pass and boot to oak kernel

Change-Id: I8aa9ca0fce804cc1682947b7e184781dd5d437f7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8641689e008c58e909606c225dddb81dc6457ae9
Original-Change-Id: I96ef8a36bc70594097e9df964934b7e3eca5d5f9
Original-Signed-off-by: jun.gao <jun.gao@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/319031
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13107
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
jun.gao 2015-12-17 16:59:55 +08:00 committed by Patrick Georgi
parent dac533725c
commit fa2ed276c3
3 changed files with 24 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/soc/mediatek/mt8173/Makefile.inc
View File

@ -17,6 +17,7 @@ ifeq ($(CONFIG_SOC_MEDIATEK_MT8173),y)
bootblock-y += bootblock.c
bootblock-$(CONFIG_SPI_FLASH) += flash_controller.c
bootblock-y += i2c.c
bootblock-y += pll.c
bootblock-y += spi.c
bootblock-y += timer.c
@ -64,7 +65,7 @@ ramstage-$(CONFIG_SPI_FLASH) += flash_controller.c
ramstage-y += soc.c mtcmos.c
ramstage-y += timer.c
ramstage-$(CONFIG_DRIVERS_UART) += uart.c
ramstage-y += pmic_wrap.c mt6391.c
ramstage-y += pmic_wrap.c mt6391.c i2c.c
ramstage-y += gpio.c
ramstage-y += wdt.c
ramstage-y += pll.c

30
src/soc/mediatek/mt8173/i2c.c
View File

@ -88,6 +88,26 @@ static inline void i2c_dma_reset(struct mt8173_i2c_dma_regs *dma_regs)
udelay(50);
}
void mtk_i2c_bus_init(uint8_t bus)
{
uint8_t sample_div;
uint8_t step_div;
uint32_t i2c_freq;
assert(bus < ARRAY_SIZE(i2c));
/* Calculate i2c frequency */
sample_div = 1;
step_div = div_round_up(I2C_CLK_HZ, (400 * KHz * sample_div * 2));
i2c_freq = I2C_CLK_HZ / (step_div * sample_div * 2);
assert(sample_div < 8 && step_div < 64 && i2c_freq < 400 * KHz &&
i2c_freq >= 380 * KHz);
/* Init i2c bus Timing register */
write32(&i2c[bus].i2c_regs->timing, (sample_div - 1) << 8 |
(step_div - 1));
}
static inline void mtk_i2c_dump_info(uint8_t bus)
{
struct mt8173_i2c_regs *regs;
@ -127,9 +147,6 @@ static uint32_t mtk_i2c_transfer(uint8_t bus, struct i2c_seg *seg,
uint32_t read_len = 0;
uint8_t *write_buffer = NULL;
uint8_t *read_buffer = NULL;
uint8_t sample_div;
uint8_t step_div;
uint32_t i2c_freq;
struct mt8173_i2c_regs *regs;
struct mt8173_i2c_dma_regs *dma_regs;
struct stopwatch sw;
@ -163,13 +180,6 @@ static uint32_t mtk_i2c_transfer(uint8_t bus, struct i2c_seg *seg,
break;
}
/* Calculate i2c frequency */
sample_div = 1;
step_div = div_round_up(I2C_CLK_HZ, (400 * KHz * sample_div * 2));
i2c_freq = I2C_CLK_HZ / (step_div * sample_div * 2);
assert(sample_div < 8 && i2c_freq < 400 * KHz && i2c_freq >= 380 * KHz);
write32(&regs->timing, (sample_div - 1) << 8 | (step_div - 1));
/* Clear interrupt status */
write32(&regs->intr_stat, I2C_TRANSAC_COMP | I2C_ACKERR |
I2C_HS_NACKERR);

2
src/soc/mediatek/mt8173/include/soc/i2c.h
View File

@ -127,4 +127,6 @@ enum {
I2C_TRANSFER_INVALID_ARGUMENT = 0xA006
};
void mtk_i2c_bus_init(uint8_t bus);
#endif /* SOC_MEDIATEK_MT8173_I2C_H */