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soc/amd/cezanne: Rename PSP_POSTCODES_ON_ESPI to PSP_INIT_ESPI 

This flag only controls eSPI init in the PSP Stage 2 Boot Loader. It
doesn't control if port 80s are written. This flag also doesn't
currently control LPC init. The PSP is currently hard coded to remove
any LPC init.

BUG=b:215425753
TEST=build guybrush

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Idf3f0dcc216df2fd15b016f9458a208b7e15c720
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61534
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Raul E Rangel 2022-02-01 11:12:33 -07:00 committed by Raul Rangel
parent 21fdd44db0
commit fa4d0510ea
2 changed files with 5 additions and 7 deletions
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10
src/soc/amd/cezanne/Kconfig
View File

@ -342,13 +342,11 @@ config PSP_DISABLE_POSTCODES
help help
Disables the output of port80 post codes from PSP. Disables the output of port80 post codes from PSP.
config PSP_POSTCODES_ON_ESPI config PSP_INIT_ESPI
bool "Use eSPI bus for PSP post codes" bool "Initialize eSPI in PSP Stage 2 Boot Loader"
default y
depends on !PSP_DISABLE_POSTCODES
help help
Select to send PSP port80 post codes on eSPI bus. Select to initialize the eSPI controller in the PSP Stage 2 Boot
If not selected, PSP port80 codes will be sent on LPC bus. Loader.
config PSP_LOAD_MP2_FW config PSP_LOAD_MP2_FW
bool bool

2
src/soc/amd/cezanne/Makefile.inc
View File

@ -94,7 +94,7 @@ ifeq ($(CONFIG_PSP_DISABLE_POSTCODES),y)
PSP_SOFTFUSE_BITS += 7 PSP_SOFTFUSE_BITS += 7
endif endif
ifeq ($(CONFIG_PSP_POSTCODES_ON_ESPI),y) ifeq ($(CONFIG_PSP_INIT_ESPI),y)
PSP_SOFTFUSE_BITS += 15 PSP_SOFTFUSE_BITS += 15
endif endif