This is the final patch to enable the msm800sev to build. This patch
adds a symbol to the model_lx/cache_as_ram.inc, and modifies some files in the mainboard directory. This patch has been tested but there is a remaining problem which I am tracking down. Expect one more patch to "get it all working". Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2638 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich
parent
5ef8b0f62b
commit
fa6c11eb40
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@ -177,6 +177,7 @@ DCacheSetupGood:
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/* Go do early init and memory setup */
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call cache_as_ram_main
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done_cache_as_ram_main:
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/* If you wanted to maintain the stack in memory you would need to set the tags as dirty
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so the wbinvd would push out the old stack contents to memory */
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@ -44,30 +44,21 @@ arch i386 end
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driver mainboard.o
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if HAVE_PIRQ_TABLE object irq_tables.o end
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#object reset.o
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##
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## Romcc output
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##
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makerule ./failover.E
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depends "$(MAINBOARD)/failover.c ./romcc"
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action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
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if HAVE_PIRQ_TABLE
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object irq_tables.o
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end
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makerule ./failover.inc
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depends "$(MAINBOARD)/failover.c ./romcc"
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action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
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if USE_DCACHE_RAM
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#compile cache_as_ram.c to auto.inc
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makerule ./cache_as_ram_auto.inc
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depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
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action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
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action "perl -e 's/.rodata/.rom.data/g' -pi $@"
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action "perl -e 's/.text/.section .rom.text/g' -pi $@"
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end
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end
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makerule ./auto.E
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depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
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action "./romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
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end
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makerule ./auto.inc
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depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
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action "./romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
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end
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##
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## Build our 16 bit and 32 bit linuxBIOS entry code
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@ -104,7 +95,7 @@ ldscript /arch/i386/lib/id.lds
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###
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if USE_FALLBACK_IMAGE
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ldscript /arch/i386/lib/failover.lds
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mainboardinit ./failover.inc
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# mainboardinit ./failover.inc
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end
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###
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@ -115,7 +106,11 @@ end
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## Setup RAM
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##
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mainboardinit cpu/x86/fpu/enable_fpu.inc
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mainboardinit ./auto.inc
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if USE_DCACHE_RAM
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mainboardinit cpu/amd/model_lx/cache_as_ram.inc
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mainboardinit ./cache_as_ram_auto.inc
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end
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##
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## Include the secondary Configuration files
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@ -124,57 +119,88 @@ dir /pc80
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config chip.h
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chip northbridge/amd/lx
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# they keep changing this. 0:f.0 5c.w to see where it is
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register "irqmap" = "0xbaba"
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register "setupflash" = "0"
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device pci_domain 0 on
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device pci 1.0 on end
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device pci 1.1 on end
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chip southbridge/amd/cs5536
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# IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK
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# SIRQ Mode = Active(Quiet) mode. Save power....
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# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK
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# How to get these? Boot linux and do this:
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# rdmsr 0x51400025
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register "lpc_serirq_enable" = "0x000010da"
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# rdmsr 0x5140004e -- polairy is high 16 bits of low 32 bits
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register "lpc_serirq_polarity" = "0x0000EF25"
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# mode is high 10 bits (determined from code)
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register "lpc_serirq_mode" = "1"
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# Don't yet know how to find this.
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register "enable_gpio_int_route" = "0x0D0C0700"
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register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
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register "enable_USBP4_device" = "0" #0: host, 1:device
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register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
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register "com1_enable" = "0"
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register "com1_address" = "0x3F8"
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register "com1_irq" = "4"
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register "com2_enable" = "0"
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register "com2_address" = "0x2F8"
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register "com2_irq" = "3"
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register "unwanted_vpci[0]" = "0" # End of list has a zero
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device pci f.0 on # ISA Bridge
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chip superio/winbond/w83627hf
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device pnp 2e.0 off # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 2e.1 off # Parallel Port
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io 0x60 = 0x378
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irq 0x70 = 7
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end
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device pnp 2e.2 on # Com1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.3 on # Com2
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 2e.5 on # Keyboard
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1
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irq 0x72 = 12
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end
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device pnp 2e.6 off # CIR
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io 0x60 = 0x100
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end
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device pnp 2e.7 off # GAME_MIDI_GIPO1
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io 0x60 = 0x220
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io 0x62 = 0x300
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irq 0x70 = 9
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end
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device pnp 2e.8 off end # GPIO2
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device pnp 2e.9 off end # GPIO3
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device pnp 2e.a off end # ACPI
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device pnp 2e.b on # HW Monitor
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io 0x60 = 0x290
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irq 0x70 = 5
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end
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end
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end
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device pci f.1 on end # Flash controller
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device pci f.2 on end # IDE controller
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device pci f.3 on end # Audio
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device pci f.4 on end # OHCI
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device pci f.5 on end # EHCI
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end
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end
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# APIC cluster is late CPU init.
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device apic_cluster 0 on
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chip cpu/amd/model_lx
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device apic 0 on end
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end
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end
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device pci_domain 0 on
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device pci 1.0 on end
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device pci 1.1 on end
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chip southbridge/amd/cs5536_lx
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register "isa_irq" = "0"
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#register "flash_irq" = "14"
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## IDE IRQ
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register "enable_ide_irq" = "0"
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register "audio_irq" = "5"
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register "usb_irq" = "7"
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register "uart0_irq" = "0"
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register "uart1_irq" = "4"
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## PCI INTA ... INTD and their GPIO pins
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## int==0: disable
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register "pci_int[0]" = "0"
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register "pci_int[1]" = "10"
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register "pci_int[2]" = "0"
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register "pci_int[3]" = "0"
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register "pci_int_pin[0]" = "0"
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register "pci_int_pin[1]" = "7"
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register "pci_int_pin[2]" = "0"
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register "pci_int_pin[3]" = "0"
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# Keyboard Emulation Logic IRQs
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# Enable keyboard IRQ2
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register "enable_kel_keyb_irq" = "0"
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# Enable mouse IRQ12
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register "enable_kel_mouse_irq" = "0"
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# Configure KEL Emulation IRQ, 0 to disable
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register "kel_emul_irq" = "0"
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device pci f.0 on end # ISA Bridge
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device pci f.1 on end # Flash controller
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device pci f.2 off end # IDE controller
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device pci f.3 on end # Audio
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device pci f.4 on end # OHCI
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device pci f.5 on end # EHCI
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end
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end
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end
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@ -21,7 +21,9 @@ uses ROM_IMAGE_SIZE
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uses ROM_SECTION_SIZE
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uses ROM_SECTION_OFFSET
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uses CONFIG_ROM_PAYLOAD_START
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uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
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uses CONFIG_COMPRESSED_PAYLOAD_LZMA
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uses CONFIG_PRECOMPRESSED_PAYLOAD
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uses PAYLOAD_SIZE
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uses _ROMBASE
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uses _RAMBASE
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@ -43,18 +45,20 @@ uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
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uses CONFIG_CONSOLE_VGA
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uses CONFIG_PCI_ROM_RUN
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uses CONFIG_VIDEO_MB
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default CONFIG_VIDEO_MB=8
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uses USE_DCACHE_RAM
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uses DCACHE_RAM_BASE
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uses DCACHE_RAM_SIZE
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## ROM_SIZE is the size of boot ROM that this board will use.
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default ROM_SIZE = 1024*1024
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default ROM_SIZE = 256*1024
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###
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### Build options
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###
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#default CONFIG_CONSOLE_VGA=1
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#default CONFIG_PCI_ROM_RUN=0
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default CONFIG_CONSOLE_VGA=0
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default CONFIG_VIDEO_MB=8
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default CONFIG_PCI_ROM_RUN=0
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##
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## Build code for the fallback boot
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##
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@ -78,9 +82,8 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
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##
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## Build code to export a programmable irq routing table
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##
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default HAVE_PIRQ_TABLE=0
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default HAVE_PIRQ_TABLE=1
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default IRQ_SLOT_COUNT=6
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#object irq_tables.o
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##
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@ -96,6 +99,13 @@ default HAVE_OPTION_TABLE=0
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default ROM_IMAGE_SIZE = 65536
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default FALLBACK_SIZE = 131072
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##
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## enable CACHE_AS_RAM specifics
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##
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default USE_DCACHE_RAM=1
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default DCACHE_RAM_BASE=0xc8000
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default DCACHE_RAM_SIZE=0x08000
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##
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## Use a small 8K stack
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##
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@ -1,3 +1,4 @@
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#if 0
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/* This file was generated by getpir.c, do not modify!
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(but if you do, please run checkpir on it to verify)
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* Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up
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@ -58,3 +59,107 @@ unsigned long write_pirq_routing_table(unsigned long addr)
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{
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return copy_pirq_routing_table(addr);
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}
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#endif
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/*
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* This file is part of the LinuxBIOS project.
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*
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* Copyright (C) 2007 Advanced Micro Devices
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <arch/pirq_routing.h>
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#include <console/console.h>
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#include <arch/io.h>
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#include <arch/pirq_routing.h>
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#include "../../../southbridge/amd/cs5536/cs5536.h"
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/* Platform IRQs */
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#define PIRQA 11
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#define PIRQB 5
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#define PIRQC 10
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#define PIRQD 10
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/* Map */
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#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */
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#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */
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#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */
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#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */
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/* Link */
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#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */
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#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */
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#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */
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#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */
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const struct irq_routing_table intel_irq_routing_table = {
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PIRQ_SIGNATURE, /* u32 signature */
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PIRQ_VERSION, /* u16 version */
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32+16*IRQ_SLOT_COUNT, /* there can be total 6 devices on the bus */
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0x00, /* Where the interrupt router lies (bus) */
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(0x0F<<3)|0x0, /* Where the interrupt router lies (dev) */
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0x00, /* IRQs devoted exclusively to PCI usage */
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0x100B, /* Vendor */
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0x002B, /* Device */
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0, /* Crap (miniport) */
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
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0x00, /* u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
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{
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/* If you change the number of entries, change the IRQ_SLOT_COUNT above! */
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/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
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{0x00,(0x01<<3)|0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */
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{0x00,(0x0F<<3)|0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */
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{0x00,(0x0C<<3)|0x0, {{L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}}, 0x1, 0x0}, /* slot1 */
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{0x00,(0x0D<<3)|0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x2, 0x0}, /* slot2 */
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{0x00,(0x0A<<3)|0x0, {{L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}}, 0x3, 0x0}, /* slot3 */
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{0x00,(0x0B<<3)|0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x4, 0x0}, /* slot4 */
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}
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};
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unsigned long write_pirq_routing_table(unsigned long addr){
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int i, j, k, num_entries;
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unsigned int pirq[4];
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uint16_t chipset_irq_map;
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uint32_t pciAddr, pirtable_end;
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struct irq_routing_table *pirq_tbl;
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pirtable_end = copy_pirq_routing_table(addr);
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/* Set up chipset IRQ steering */
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pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
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chipset_irq_map = (PIRQD << 12 | PIRQC << 8 | PIRQB << 4 | PIRQA);
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printk_debug("%s(%08X, %04X)\n", __FUNCTION__, pciAddr, chipset_irq_map);
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outl(pciAddr & ~3, 0xCF8);
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outl(chipset_irq_map, 0xCFC);
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pirq_tbl = (struct irq_routing_table *)(addr);
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num_entries = (pirq_tbl->size - 32)/16;
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/* Set PCI IRQs */
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for (i=0; i < num_entries; i++){
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printk_debug("PIR Entry %d Dev/Fn: %X Slot: %d\n", i, pirq_tbl->slots[i].devfn, pirq_tbl->slots[i].slot);
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for (j = 0; j < 4; j++){
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printk_debug("INT: %c bitmap: %x ", 'A'+j, pirq_tbl->slots[i].irq[j].bitmap);
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for (k = 0; (!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 1)) && (pirq_tbl->slots[i].irq[j].bitmap != 0); k++); /* finds lsb in bitmap to IRQ# */
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pirq[j] = k;
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printk_debug("PIRQ: %d\n", k);
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}
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pci_assign_irqs(pirq_tbl->slots[i].bus, pirq_tbl->slots[i].devfn, pirq); /* bus, device, slots IRQs for {A,B,C,D} */
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}
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/* put the PIR table in memory and checksum */
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return pirtable_end;
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}
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@ -6,54 +6,140 @@
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#include <arch/io.h>
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#include <cpu/x86/msr.h>
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#include <cpu/amd/lxdef.h>
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#include "../../../southbridge/amd/cs5536/cs5536.h"
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#include "chip.h"
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#define DIVIL_LBAR_GPIO 0x5140000c
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static void init_gpio()
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{
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/* Print the platform configuration */
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void print_conf(void) {
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#if DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR
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int i;
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unsigned long iol;
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msr_t msr;
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printk_debug("Initializing GPIO module...\n");
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||||
|
||||
// initialize the GPIO LBAR
|
||||
msr.lo = GPIO_BASE;
|
||||
msr.hi = 0x0000f001;
|
||||
wrmsr(DIVIL_LBAR_GPIO, msr);
|
||||
msr = rdmsr(DIVIL_LBAR_GPIO);
|
||||
printk_debug("DIVIL_LBAR_GPIO set to 0x%08x 0x%08x\n", msr.hi, msr.lo);
|
||||
int cpu_msr_defs[] = { CPU_BC_L2_CONF, CPU_IM_CONFIG,
|
||||
CPU_DM_CONFIG0, CPU_RCONF_DEFAULT,
|
||||
CPU_RCONF_BYPASS, CPU_RCONF_A0_BF, CPU_RCONF_C0_DF, CPU_RCONF_E0_FF,
|
||||
CPU_RCONF_SMM, CPU_RCONF_DMM, GLCP_DELAY_CONTROLS, GL_END
|
||||
};
|
||||
|
||||
int gliu0_msr_defs[] = {MSR_GLIU0_BASE1, MSR_GLIU0_BASE2, MSR_GLIU0_BASE4, MSR_GLIU0_BASE5, MSR_GLIU0_BASE6,
|
||||
GLIU0_P2D_BMO_0, GLIU0_P2D_BMO_1, MSR_GLIU0_SYSMEM,
|
||||
GLIU0_P2D_RO_0, GLIU0_P2D_RO_1, GLIU0_P2D_RO_2, MSR_GLIU0_SHADOW,
|
||||
GLIU0_IOD_BM_0, GLIU0_IOD_BM_1, GLIU0_IOD_BM_2,
|
||||
GLIU0_IOD_SC_0, GLIU0_IOD_SC_1, GLIU0_IOD_SC_2, GLIU0_IOD_SC_3, GLIU0_IOD_SC_4, GLIU0_IOD_SC_5,
|
||||
GLIU0_GLD_MSR_COH, GL_END
|
||||
};
|
||||
|
||||
int gliu1_msr_defs[] = {MSR_GLIU1_BASE1, MSR_GLIU1_BASE2, MSR_GLIU1_BASE3, MSR_GLIU1_BASE4, MSR_GLIU1_BASE5, MSR_GLIU1_BASE6,
|
||||
MSR_GLIU1_BASE7, MSR_GLIU1_BASE8, MSR_GLIU1_BASE9, MSR_GLIU1_BASE10,
|
||||
GLIU1_P2D_R_0, GLIU1_P2D_R_1, GLIU1_P2D_R_2, GLIU1_P2D_R_3, MSR_GLIU1_SHADOW,
|
||||
GLIU1_IOD_BM_0, GLIU1_IOD_BM_1, GLIU1_IOD_BM_2,
|
||||
GLIU1_IOD_SC_0, GLIU1_IOD_SC_1, GLIU1_IOD_SC_2, GLIU1_IOD_SC_3,
|
||||
GLIU1_GLD_MSR_COH, GL_END
|
||||
};
|
||||
|
||||
int rconf_msr[] = { CPU_RCONF0, CPU_RCONF1, CPU_RCONF2, CPU_RCONF3, CPU_RCONF4,
|
||||
CPU_RCONF5, CPU_RCONF6, CPU_RCONF7, GL_END
|
||||
};
|
||||
|
||||
int cs5536_msr[] = { MDD_LBAR_GPIO, MDD_LBAR_FLSH0, MDD_LBAR_FLSH1, MDD_LEG_IO, MDD_PIN_OPT,
|
||||
MDD_IRQM_ZLOW, MDD_IRQM_ZHIGH, MDD_IRQM_PRIM, GL_END
|
||||
};
|
||||
|
||||
int pci_msr[] = { GLPCI_CTRL, GLPCI_ARB, GLPCI_REN, GLPCI_A0_BF, GLPCI_C0_DF, GLPCI_E0_FF,
|
||||
GLPCI_RC0, GLPCI_RC1, GLPCI_RC2, GLPCI_RC3, GLPCI_ExtMSR, GLPCI_SPARE,
|
||||
GL_END
|
||||
};
|
||||
|
||||
int dma_msr[] = { MDD_DMA_MAP, MDD_DMA_SHAD1, MDD_DMA_SHAD2, MDD_DMA_SHAD3, MDD_DMA_SHAD4,
|
||||
MDD_DMA_SHAD5, MDD_DMA_SHAD6, MDD_DMA_SHAD7, MDD_DMA_SHAD8,
|
||||
MDD_DMA_SHAD9, GL_END
|
||||
};
|
||||
|
||||
|
||||
printk_debug("---------- CPU ------------\n");
|
||||
|
||||
for(i = 0; cpu_msr_defs[i] != GL_END; i++) {
|
||||
msr = rdmsr(cpu_msr_defs[i]);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", cpu_msr_defs[i], msr.hi, msr.lo);
|
||||
}
|
||||
|
||||
printk_debug("---------- GLIU 0 ------------\n");
|
||||
|
||||
for(i = 0; gliu0_msr_defs[i] != GL_END; i++) {
|
||||
msr = rdmsr(gliu0_msr_defs[i]);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", gliu0_msr_defs[i], msr.hi, msr.lo);
|
||||
}
|
||||
|
||||
printk_debug("---------- GLIU 1 ------------\n");
|
||||
|
||||
for(i = 0; gliu1_msr_defs[i] != GL_END; i++) {
|
||||
msr = rdmsr(gliu1_msr_defs[i]);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", gliu1_msr_defs[i], msr.hi, msr.lo);
|
||||
}
|
||||
|
||||
printk_debug("---------- RCONF ------------\n");
|
||||
|
||||
for(i = 0; rconf_msr[i] != GL_END; i++) {
|
||||
msr = rdmsr(rconf_msr[i]);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", rconf_msr[i], msr.hi, msr.lo);
|
||||
}
|
||||
|
||||
printk_debug("---------- VARIA ------------\n");
|
||||
msr = rdmsr(0x51300010);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51300010, msr.hi, msr.lo);
|
||||
|
||||
msr = rdmsr(0x51400015);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51400015, msr.hi, msr.lo);
|
||||
|
||||
printk_debug("---------- DIVIL IRQ ------------\n");
|
||||
msr = rdmsr(MDD_IRQM_YLOW);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YLOW, msr.hi, msr.lo);
|
||||
msr = rdmsr(MDD_IRQM_YHIGH);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YHIGH, msr.hi, msr.lo);
|
||||
msr = rdmsr(MDD_IRQM_ZLOW);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZLOW, msr.hi, msr.lo);
|
||||
msr = rdmsr(MDD_IRQM_ZHIGH);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZHIGH, msr.hi, msr.lo);
|
||||
|
||||
|
||||
printk_debug("---------- PCI ------------\n");
|
||||
|
||||
for(i = 0; pci_msr[i] != GL_END; i++) {
|
||||
msr = rdmsr(pci_msr[i]);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", pci_msr[i], msr.hi, msr.lo);
|
||||
}
|
||||
|
||||
printk_debug("---------- LPC/UART DMA ------------\n");
|
||||
|
||||
for(i = 0; dma_msr[i] != GL_END; i++) {
|
||||
msr = rdmsr(dma_msr[i]);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", dma_msr[i], msr.hi, msr.lo);
|
||||
}
|
||||
|
||||
printk_debug("---------- CS5536 ------------\n");
|
||||
|
||||
for(i = 0; cs5536_msr[i] != GL_END; i++) {
|
||||
msr = rdmsr(cs5536_msr[i]);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", cs5536_msr[i], msr.hi, msr.lo);
|
||||
}
|
||||
|
||||
iol = inl(GPIOL_INPUT_ENABLE);
|
||||
printk_debug("IOR 0x%08X is now 0x%08X\n", GPIOL_INPUT_ENABLE, iol);
|
||||
iol = inl(GPIOL_EVENTS_ENABLE);
|
||||
printk_debug("IOR 0x%08X is now 0x%08X\n", GPIOL_EVENTS_ENABLE, iol);
|
||||
iol = inl(GPIOL_INPUT_INVERT_ENABLE);
|
||||
printk_debug("IOR 0x%08X is now 0x%08X\n", GPIOL_INPUT_INVERT_ENABLE, iol);
|
||||
iol = inl(GPIO_MAPPER_X);
|
||||
printk_debug("IOR 0x%08X is now 0x%08X\n", GPIO_MAPPER_X, iol);
|
||||
#endif //DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR
|
||||
}
|
||||
|
||||
static void init(struct device *dev) {
|
||||
|
||||
static void init(struct device *dev)
|
||||
{
|
||||
unsigned bus = 0;
|
||||
unsigned devNic = PCI_DEVFN(0xd, 0);
|
||||
unsigned devUsb = PCI_DEVFN(0xf, 4);
|
||||
device_t usb = NULL, nic = NULL;
|
||||
unsigned char irqUsb = 0xa, irqNic = 0xb;
|
||||
printk_debug("MSM800SEV ENTER %s\n", __FUNCTION__);
|
||||
|
||||
printk_debug("DIGITALLOGIC MSM800SSEV ENTER %s\n", __FUNCTION__);
|
||||
|
||||
#if 0
|
||||
// FIXME: do we need to initialize USB OHCI this way?
|
||||
printk_debug("%s (%x,%x) set USB PCI interrupt line to %d\n",
|
||||
__FUNCTION__, bus, devUsb, irqUsb);
|
||||
|
||||
// initialize the USB controller
|
||||
usb = dev_find_slot(bus, devUsb);
|
||||
if (!usb) printk_err("Could not find USB\n");
|
||||
else pci_write_config8(usb, PCI_INTERRUPT_LINE, irqUsb);
|
||||
|
||||
printk_debug("%s (%x,%x) set NIC PCI interrupt line to %d\n",
|
||||
__FUNCTION__, bus, devNic, irqNic);
|
||||
|
||||
// initialize theEEPRO 100
|
||||
nic = dev_find_slot(bus, devNic);
|
||||
if (!nic) printk_err("Could not find USB\n");
|
||||
else pci_write_config8(nic, PCI_INTERRUPT_LINE, irqNic);
|
||||
#endif
|
||||
init_gpio();
|
||||
|
||||
printk_debug("DIGITALLOGIC MSM800SSEV EXIT %s\n", __FUNCTION__);
|
||||
printk_debug("MSM800SEV EXIT %s\n", __FUNCTION__);
|
||||
}
|
||||
|
||||
static void enable_dev(struct device *dev)
|
||||
|
|
|
|||
|
|
@ -7,8 +7,9 @@ option CONFIG_COMPRESSED_PAYLOAD_NRV2B=0
|
|||
|
||||
## ROM_SIZE is the total number of bytes allocated for LinuxBIOS use
|
||||
## (normal AND fallback images and payloads).
|
||||
## leave 64k for vsa and 32K for video ROM
|
||||
option ROM_SIZE = 1024*1024 - 64*1024 - 32 * 1024
|
||||
## leave 36k for vsa
|
||||
##
|
||||
option ROM_SIZE = 1024*1024 - 36 * 1024
|
||||
|
||||
## ROM_IMAGE_SIZE is the maximum number of bytes allowed for a LinuxBIOS image,
|
||||
## not including any payload.
|
||||
|
|
|
|||
Loading…
Reference in New Issue