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Persimmon: adapt PCIe reset code copied from Inagua to actually match Persimmon 

Comparing Persimmon and Inagua schematics and Coreboot code show the PCIe reset
code has been blindly copied even though it doesn't suit the Persimmon at all.

The Inagua can employ GPIOs 21, 25, 02 to manually reset devices on APU PCIe
lanes 0/1, 2, 3 respectively. (Appearently the motivation for this is to revive
buggy PCIe gen1 devices which got confused by PCIe gen2 signal training.)

However the Persimmon not only doesn't support this, it even needs these 3 pins
for the PCI interface! Instead it uses GPIO50 to reset devices on lanes 0-2 all
at once. Lane 3 is unconnected anyway.

This patch adapts the Persimmon mainboard code according to the DB-FT1 rev. D
schematics.

Change-Id: I05a657d9bf8cc59acc4f5174eb20375165c860c7
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Reviewed-on: http://review.coreboot.org/2446
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
This commit is contained in:
Jens Rottmann 2013-02-18 19:40:33 +01:00 committed by Peter Stuge
parent 686dc0d66b
commit fa8702cf2a
3 changed files with 12 additions and 51 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

42
src/mainboard/amd/persimmon/BiosCallOuts.c
View File

@ -562,50 +562,18 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
switch (ResetInfo->ResetId) switch (ResetInfo->ResetId)
{ {
case 4: case 46: // GPIO50 = SBGPIO_PCIE_RST# affects LAN0, LAN1, PCIe slot
switch (ResetInfo->ResetControl) { switch (ResetInfo->ResetControl) {
case AssertSlotReset: case AssertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50);
Data8 &= ~(UINT8)BIT6 ; Data8 &= ~(UINT8)BIT6 ;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 Write64Mem8(GpioMmioAddr+SB_GPIO_REG50, Data8);
Status = AGESA_SUCCESS; Status = AGESA_SUCCESS;
break; break;
case DeassertSlotReset: case DeassertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50);
Data8 |= BIT6 ; Data8 |= BIT6 ;
Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 Write64Mem8 (GpioMmioAddr+SB_GPIO_REG50, Data8);
Status = AGESA_SUCCESS;
break;
}
break;
case 6:
switch (ResetInfo->ResetControl) {
case AssertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
Data8 &= ~(UINT8)BIT6 ;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25
Status = AGESA_SUCCESS;
break;
case DeassertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
Data8 |= BIT6 ;
Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25
Status = AGESA_SUCCESS;
break;
}
break;
case 7:
switch (ResetInfo->ResetControl) {
case AssertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
Data8 &= ~(UINT8)BIT6 ;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02
Status = AGESA_SUCCESS;
break;
case DeassertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
Data8 |= BIT6 ;
Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02
Status = AGESA_SUCCESS; Status = AGESA_SUCCESS;
break; break;
} }

11
src/mainboard/amd/persimmon/BiosCallOuts.h
View File

@ -69,12 +69,7 @@ AGESA_STATUS BiosHookBeforeDramInitRecovery (UINT32 Func, UINT32 Data, VOID *Con
AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr); AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
/* PCIE slot reset control */ /* PCIE slot reset control */
AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr); AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
#define SB_GPIO_REG02 2
#define SB_GPIO_REG09 9 #define SB_GPIO_REG50 50
#define SB_GPIO_REG10 10
#define SB_GPIO_REG15 15
#define SB_GPIO_REG17 17
#define SB_GPIO_REG21 21
#define SB_GPIO_REG25 25
#define SB_GPIO_REG28 28
#endif //_BIOS_CALLOUT_H_ #endif //_BIOS_CALLOUT_H_

10
src/mainboard/amd/persimmon/PlatformGnbPcie.c
View File

@ -60,28 +60,26 @@ PCIe_PORT_DESCRIPTOR PortList [] = {
{ {
0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4),
PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4) PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 46)
}, },
#if 1
// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
{ {
0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5),
PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 5) PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 46)
}, },
// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
{ {
0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6),
PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6) PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 46)
}, },
// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7),
PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7) PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 0)
}, },
#endif
// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
{ {
DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array