RS780 DDI Lanes configure support,
and remove RS780 get_cpu_rev(). Signed-off-by: Kerry She <kerry.she@amd.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6560 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Kerry She
Kerry She
parent
eb995c209c
commit
faafd14fe0
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@ -33,6 +33,8 @@ struct southbridge_amd_rs780_config
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u8 gfx_compliance; /* whether support compliance? */
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u8 gfx_reconfiguration; /* Dynamic Lind Width Control */
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u8 gfx_link_width; /* Desired width of lane 2 */
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u8 gfx_pcie_config; /* GFX PCIE Modes */
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u8 gfx_ddi_config; /* GFX DDI Modes */
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};
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struct chip_operations;
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extern struct chip_operations southbridge_amd_rs780_ops;
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@ -142,32 +142,6 @@ static void set_nbmc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,
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}
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}
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static void get_cpu_rev(void)
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{
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u32 eax;
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eax = cpuid_eax(1);
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printk(BIOS_INFO, "get_cpu_rev EAX=0x%x.\n", eax);
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if (eax <= 0xfff)
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printk(BIOS_INFO, "CPU Rev is K8_Cx.\n");
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else if (eax <= 0x10fff)
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printk(BIOS_INFO, "CPU Rev is K8_Dx.\n");
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else if (eax <= 0x20fff)
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printk(BIOS_INFO, "CPU Rev is K8_Ex.\n");
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else if (eax <= 0x40fff)
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printk(BIOS_INFO, "CPU Rev is K8_Fx.\n");
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else if (eax == 0x60fb1 || eax == 0x60f81) /*These two IDS are exception, they are G1. */
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printk(BIOS_INFO, "CPU Rev is K8_G1.\n");
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else if (eax <= 0X60FF0)
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printk(BIOS_INFO, "CPU Rev is K8_G0.\n");
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else if (eax <= 0x100000)
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printk(BIOS_INFO, "CPU Rev is K8_G1.\n");
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else if (eax <= 0x100f00)
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printk(BIOS_INFO, "CPU Rev is Fam 10.\n");
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else
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printk(BIOS_INFO, "CPU Rev is K8_10.\n");
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}
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static u8 is_famly10(void)
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{
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return (cpuid_eax(1) & 0xff00000) != 0;
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@ -630,6 +604,13 @@ static void rs780_por_init(device_t nb_dev)
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/* ATINB_CLKCFG_PORT_TABLE */
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/* rs780 A11 SB Link full swing? */
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/* SET NB_MISC_REG01 BIT8 to Enable HDMI, reference CIMX_5_9_3 NBPOR_InitPOR(),
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* then the accesses to internal graphics IO space 0x60/0x64, are forwarded to
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* nbconfig:0x60/0x64
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*/
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set_nbmisc_enable_bits(nb_dev, 0x01, ~(1 << 8), (1 << 8));
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}
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/* enable CFG access to Dev8, which is the SB P2P Bridge */
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@ -647,8 +628,6 @@ static void rs780_early_setup(void)
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device_t nb_dev = PCI_DEV(0, 0, 0);
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printk(BIOS_INFO, "rs780_early_setup()\n");
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get_cpu_rev();
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/* The printk(BIOS_INFO, s) below cause the system unstable. */
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switch (get_nb_rev(nb_dev)) {
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case REV_RS780_A11:
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@ -303,6 +303,43 @@ static void ProgramMMIO(MMIORANGE *pMMIO, u8 LinkID, u8 Attribute)
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}
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#endif
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#define GFX_CONFIG_DDI1 0x04
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#define GFX_CONFIG_DDI2 0x08
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#define GFX_CONFIG_DDI (GFX_CONFIG_DDI1 | GFX_CONFIG_DDI2)
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/**
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* Force poweron pads for lanes used for DDI
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* reference CIMx PCIEL_PowerOnDDILanes()
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*
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* Inactive B_PRX_PDNB_FDIS B_PTX_PDNB_FDIS
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* Lanes
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* Lanes 0-1 Bit 8 Bit 0
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* Lanes 2-3 Bit 9 Bit 1
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* Lanes 4-5 Bit 10 Bit 2
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* Lanes 6-7 Bit 11 Bit 3
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* Lanes 8-9 Bit 12 Bit 4
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* Lanes 10-11 Bit 13 Bit 5
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* Lanes 12-13 Bit 14 Bit 6
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* Lanes 14-15 Bit 15 Bit 7
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*/
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static void poweron_ddi_lanes(device_t nb_dev)
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{
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u8 i;
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u32 gfx_cfg = 0;
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u32 ddi_pads = 0;
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ddi_pads = ~(nbpcie_ind_read_index(nb_dev, 0x65)); /* save original setting */
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gfx_cfg = nbmisc_read_index(nb_dev, 0x74);
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for (i = 0; i < 3 ; i++) {
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if (gfx_cfg & GFX_CONFIG_DDI) {
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ddi_pads |= (3 << (i * 2));
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}
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gfx_cfg >>= 8;
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}
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ddi_pads |= ddi_pads << 8; /* both TX and RX */
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nbpcie_ind_write_index(nb_dev, 0x65, ~ddi_pads);
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}
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static void internal_gfx_pci_dev_init(struct device *dev)
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{
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unsigned char * bpointer;
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@ -535,6 +572,9 @@ static void internal_gfx_pci_dev_init(struct device *dev)
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}
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}
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/* Poweron DDI Lanes */
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poweron_ddi_lanes(nb_dev);
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/* Transfer the Table to VBIOS. */
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pointer = (u32 *)&vgainfo;
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for(i=0; i<sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2); i+=4)
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@ -1111,6 +1151,147 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port)
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/* step 2, TMDS, (only need if CMOS option is enabled) */
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if (cfg->gfx_tmds) {
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/**
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* PCIe Initialization for DDI.
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* The VBIOS/Driver is responsible for DDI programming sequence,
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* The SBIOS is responsible for programming the lane and clock muxing specific to each case.
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* Refer to RPR Chapter 7: "PCIe Initialization for DDI".
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* Note: This programming must be done before hold training is released.
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*/
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switch (cfg->gfx_pcie_config) {
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case 1: /* 1x16 GFX -default case, no programming required */
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break;
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case 2: /* 1x8 GFX on Lanes 0-7 */
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case 5: /* 1x4 GPP on Lanes 0-3 */
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set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 6, 0x1 << 6); /* Disables PCIe mode on PHY Lanes 8-11 */
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set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 7, 0x1 << 7); /* Disables PCIe mode on PHY Lanes 12-15 */
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break;
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case 3: /* 1x8 on Lanes 8-15 */
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case 7: /* 1x4 GPP on Lanes 8-11 */
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/* TXCLK */
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set_nbmisc_enable_bits(nb_dev, 0x07, 1 << 16, 1 << 16);
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set_nbmisc_enable_bits(nb_dev, 0x07, 0xF << 12, 0xF << 12);
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set_nbmisc_enable_bits(nb_dev, 0x07, 0x3 << 24, 0x2 << 24);
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set_nbmisc_enable_bits(nb_dev, 0x28, 0x3 << 0, 0x0 << 0);
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/* RXCLK */
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set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 8, 0x2 << 8);
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set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 10, 0x2 << 10);
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set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 12, 0x2 << 12);
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set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 14, 0x2 << 14);
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/* TX Lane Muxing */
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set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 2, 0x1 << 2);
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set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 3, 0x1 << 3);
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set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 4, 0x1 << 4);
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set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 5, 0x1 << 5);
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break;
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case 4: /* 2x8 */
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case 10: /* 1x4 GPP on Lanes 0-3 and 1x4 GPP on Lanes 8-11 */
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case 14: /* 1x8 GFX on Lanes 0-7 and 1x4 GPP on Lanes 8-11 */
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case 17: /* 1x4 GPP on Lanes 0-3 and 1x8 GFX on Lanes 8-15 */
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/* Set dual slot configuration */
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set_nbmisc_enable_bits(nb_dev, 0x08, 0xF << 8, 0x5 << 8);
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break;
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case 9: /* PCIe 2x4 GPPs on Lanes 0-7 */
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case 6: /* PCIe 1x4 GPP on Lanes 4-7 */
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/* Set dual slot configuration */
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set_nbmisc_enable_bits(nb_dev, 0x08, 0xF << 8, 0x5 << 8);
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/* TXCLK */
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set_nbmisc_enable_bits(nb_dev, 0x07, 1 << 16, 0 << 16);
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set_nbmisc_enable_bits(nb_dev, 0x07, 0xF << 12, 0x0 << 12);
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set_nbmisc_enable_bits(nb_dev, 0x07, 0x3 << 20, 0x0 << 20);
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set_nbmisc_enable_bits(nb_dev, 0x28, 0x1 << 0, 0x0 << 0);
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/* RXCLK */
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set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 8, 0x0 << 8);
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set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 10, 0x1 << 10);
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set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 12, 0x3 << 12);
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set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 14, 0x0 << 14);
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/* TX Lane Muxing */
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set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 1, 0x1 << 1);
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set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 6, 0x1 << 6);
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set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 7, 0x1 << 7);
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break;
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case 13: /* 2x4 GPPs on Lanes 8-15 */
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case 8: /* 1x4 GPP on Lanes 12-15 */
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/* Set dual slot configuration */
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set_nbmisc_enable_bits(nb_dev, 0x08, 0xF << 8, 0x5 << 8);
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/* TXCLK */
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set_nbmisc_enable_bits(nb_dev, 0x07, 1 << 16, 1 << 16);
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set_nbmisc_enable_bits(nb_dev, 0x07, 0xF << 12, 0xF << 12);
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set_nbmisc_enable_bits(nb_dev, 0x07, 0x3 << 24, 0x2 << 24);
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set_nbmisc_enable_bits(nb_dev, 0x28, 0x3 << 0, 0x3 << 0);
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/* RXCLK */
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set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 8, 0x2 << 8);
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set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 10, 0x3 << 10);
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set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 12, 0x1 << 12);
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set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 14, 0x2 << 14);
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/* TX Lane Muxing */
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set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 2, 0x1 << 2);
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set_nbmisc_enable_bits(nb_dev, 0x28, 0x1 << 14, 0x1 << 14);
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set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 4, 0x1 << 4);
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set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 5, 0x1 << 5);
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break;
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case 15: /* 1x8 GFX on Lanes 0-7 and 1x4 GPP on Lanes 12-15 */
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case 11: /* 1x4 GPP on Lanes 0-3 and 1x4 GPP on Lanes 12-15 */
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/* Set dual slot configuration */
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set_nbmisc_enable_bits(nb_dev, 0x08, 0xF << 8, 0x5 << 8);
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/* TXCLK */
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set_nbmisc_enable_bits(nb_dev, 0x07, 1 << 16, 0 << 16);
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set_nbmisc_enable_bits(nb_dev, 0x07, 0xF << 12, 0x0 << 12);
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set_nbmisc_enable_bits(nb_dev, 0x07, 0x3 << 20, 0x0 << 20);
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set_nbmisc_enable_bits(nb_dev, 0x28, 0x3 << 0, 0x1 << 0);
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/* RXCLK */
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set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 8, 0x0 << 8);
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set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 10, 0x0 << 10);
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set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 12, 0x1 << 12);
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set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 14, 0x3 << 14);
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/* TX Lane Muxing */
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set_nbmisc_enable_bits(nb_dev, 0x28, 0x1 << 14, 0x1 << 14);
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set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 6, 0x1 << 6);
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break;
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case 16: /* 1x8 GFX on Lanes 8-15 and 1x4 GPP on Lanes 4-7 */
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case 12: /* 1x4 GPP on Lanes 4-7 and 1x8 GFX on Lanes 8-15 */
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/* Set dual slot configuration */
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set_nbmisc_enable_bits(nb_dev, 0x08, 0xF << 8, 0x5 << 8);
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/* TXCLK */
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set_nbmisc_enable_bits(nb_dev, 0x07, 1 << 16, 1 << 16);
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set_nbmisc_enable_bits(nb_dev, 0x07, 0xF << 12, 0xF << 12);
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set_nbmisc_enable_bits(nb_dev, 0x07, 0x3 << 24, 0x2 << 24);
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set_nbmisc_enable_bits(nb_dev, 0x07, 0x3 << 22, 0x2 << 22);
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set_nbmisc_enable_bits(nb_dev, 0x28, 0x3 << 0, 0x2 << 0);
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/* RXCLK */
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set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 8, 0x2 << 8);
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set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 10, 0x2 << 10);
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set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 12, 0x3 << 12);
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set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 14, 0x1 << 14);
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/* TX Lane Muxing */
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set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 2, 0x1 << 2);
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set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 3, 0x1 << 3);
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set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 1, 0x1 << 1);
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set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 4, 0x1 << 4);
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break;
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default:
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printk(BIOS_INFO, "Incorrect configuration of external GFX slot.\n");
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break;
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}
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/* DDI Configuration */
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switch (cfg->gfx_ddi_config) {
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case 1: /* DDI_SL lanes0-3 */
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nbmisc_write_index(nb_dev, 0x74, GFX_CONFIG_DDI);
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break;
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case 2: /* DDI_SL lanes4-7 */
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nbmisc_write_index(nb_dev, 0x74, (GFX_CONFIG_DDI << 8));
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break;
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case 5: /* DDI_SL lanes0-4, lanes4-7 */
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nbmisc_write_index(nb_dev, 0x74, (GFX_CONFIG_DDI << 8) | GFX_CONFIG_DDI);
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break;
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case 6: /* DDI_DL lanes0-7 */
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nbmisc_write_index(nb_dev, 0x74, (GFX_CONFIG_DDI << 8) | GFX_CONFIG_DDI);
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break;
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default:
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printk(BIOS_INFO, "Incorrect configuration of external GFX slot.\n");
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break;
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}
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}
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#if 1 /* external clock mode */
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@ -1123,8 +1304,6 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port)
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/* 5.9.1.3 Selects the GFX REFCLK to be the source for PLL A. */
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/* 5.9.1.4 Selects the GFX REFCLK to be the source for PLL B. */
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/* 5.9.1.5 Selects the GFX REFCLK to be the source for PLL C. */
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set_nbmisc_enable_bits(nb_dev, 0x28, 3 << 6 | 3 << 8 | 3 << 10,
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1 << 6 | 1 << 8 | 1 << 10);
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reg32 = nbmisc_read_index(nb_dev, 0x28);
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printk(BIOS_DEBUG, "misc 28 = %x\n", reg32);
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