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RS780 DDI Lanes configure support, 

and remove RS780 get_cpu_rev().

Signed-off-by: Kerry She <kerry.she@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6560 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Kerry She 2011-05-07 08:51:32 +00:00 committed by Kerry She
parent eb995c209c
commit faafd14fe0
3 changed files with 190 additions and 30 deletions
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2
src/southbridge/amd/rs780/chip.h
View File

@ -33,6 +33,8 @@ struct southbridge_amd_rs780_config
u8 gfx_compliance; /* whether support compliance? */ u8 gfx_compliance; /* whether support compliance? */
u8 gfx_reconfiguration; /* Dynamic Lind Width Control */ u8 gfx_reconfiguration; /* Dynamic Lind Width Control */
u8 gfx_link_width; /* Desired width of lane 2 */ u8 gfx_link_width; /* Desired width of lane 2 */
u8 gfx_pcie_config; /* GFX PCIE Modes */
u8 gfx_ddi_config; /* GFX DDI Modes */
}; };
struct chip_operations; struct chip_operations;
extern struct chip_operations southbridge_amd_rs780_ops; extern struct chip_operations southbridge_amd_rs780_ops;

35
src/southbridge/amd/rs780/early_setup.c
View File

@ -142,32 +142,6 @@ static void set_nbmc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,
} }
} }
static void get_cpu_rev(void)
{
u32 eax;
eax = cpuid_eax(1);
printk(BIOS_INFO, "get_cpu_rev EAX=0x%x.\n", eax);
if (eax <= 0xfff)
printk(BIOS_INFO, "CPU Rev is K8_Cx.\n");
else if (eax <= 0x10fff)
printk(BIOS_INFO, "CPU Rev is K8_Dx.\n");
else if (eax <= 0x20fff)
printk(BIOS_INFO, "CPU Rev is K8_Ex.\n");
else if (eax <= 0x40fff)
printk(BIOS_INFO, "CPU Rev is K8_Fx.\n");
else if (eax == 0x60fb1 || eax == 0x60f81) /*These two IDS are exception, they are G1. */
printk(BIOS_INFO, "CPU Rev is K8_G1.\n");
else if (eax <= 0X60FF0)
printk(BIOS_INFO, "CPU Rev is K8_G0.\n");
else if (eax <= 0x100000)
printk(BIOS_INFO, "CPU Rev is K8_G1.\n");
else if (eax <= 0x100f00)
printk(BIOS_INFO, "CPU Rev is Fam 10.\n");
else
printk(BIOS_INFO, "CPU Rev is K8_10.\n");
}
static u8 is_famly10(void) static u8 is_famly10(void)
{ {
return (cpuid_eax(1) & 0xff00000) != 0; return (cpuid_eax(1) & 0xff00000) != 0;
@ -630,6 +604,13 @@ static void rs780_por_init(device_t nb_dev)
/* ATINB_CLKCFG_PORT_TABLE */ /* ATINB_CLKCFG_PORT_TABLE */
/* rs780 A11 SB Link full swing? */ /* rs780 A11 SB Link full swing? */
/* SET NB_MISC_REG01 BIT8 to Enable HDMI, reference CIMX_5_9_3 NBPOR_InitPOR(),
* then the accesses to internal graphics IO space 0x60/0x64, are forwarded to
* nbconfig:0x60/0x64
*/
set_nbmisc_enable_bits(nb_dev, 0x01, ~(1 << 8), (1 << 8));
} }
/* enable CFG access to Dev8, which is the SB P2P Bridge */ /* enable CFG access to Dev8, which is the SB P2P Bridge */
@ -647,8 +628,6 @@ static void rs780_early_setup(void)
device_t nb_dev = PCI_DEV(0, 0, 0); device_t nb_dev = PCI_DEV(0, 0, 0);
printk(BIOS_INFO, "rs780_early_setup()\n"); printk(BIOS_INFO, "rs780_early_setup()\n");
get_cpu_rev();
/* The printk(BIOS_INFO, s) below cause the system unstable. */ /* The printk(BIOS_INFO, s) below cause the system unstable. */
switch (get_nb_rev(nb_dev)) { switch (get_nb_rev(nb_dev)) {
case REV_RS780_A11: case REV_RS780_A11:

183
src/southbridge/amd/rs780/gfx.c
View File

@ -303,6 +303,43 @@ static void ProgramMMIO(MMIORANGE *pMMIO, u8 LinkID, u8 Attribute)
} }
#endif #endif
#define GFX_CONFIG_DDI1 0x04
#define GFX_CONFIG_DDI2 0x08
#define GFX_CONFIG_DDI (GFX_CONFIG_DDI1 | GFX_CONFIG_DDI2)
/**
* Force poweron pads for lanes used for DDI
* reference CIMx PCIEL_PowerOnDDILanes()
*
* Inactive B_PRX_PDNB_FDIS B_PTX_PDNB_FDIS
* Lanes
* Lanes 0-1 Bit 8 Bit 0
* Lanes 2-3 Bit 9 Bit 1
* Lanes 4-5 Bit 10 Bit 2
* Lanes 6-7 Bit 11 Bit 3
* Lanes 8-9 Bit 12 Bit 4
* Lanes 10-11 Bit 13 Bit 5
* Lanes 12-13 Bit 14 Bit 6
* Lanes 14-15 Bit 15 Bit 7
*/
static void poweron_ddi_lanes(device_t nb_dev)
{
u8 i;
u32 gfx_cfg = 0;
u32 ddi_pads = 0;
ddi_pads = ~(nbpcie_ind_read_index(nb_dev, 0x65)); /* save original setting */
gfx_cfg = nbmisc_read_index(nb_dev, 0x74);
for (i = 0; i < 3 ; i++) {
if (gfx_cfg & GFX_CONFIG_DDI) {
ddi_pads |= (3 << (i * 2));
}
gfx_cfg >>= 8;
}
ddi_pads |= ddi_pads << 8; /* both TX and RX */
nbpcie_ind_write_index(nb_dev, 0x65, ~ddi_pads);
}
static void internal_gfx_pci_dev_init(struct device *dev) static void internal_gfx_pci_dev_init(struct device *dev)
{ {
unsigned char * bpointer; unsigned char * bpointer;
@ -535,6 +572,9 @@ static void internal_gfx_pci_dev_init(struct device *dev)
} }
} }
/* Poweron DDI Lanes */
poweron_ddi_lanes(nb_dev);
/* Transfer the Table to VBIOS. */ /* Transfer the Table to VBIOS. */
pointer = (u32 *)&vgainfo; pointer = (u32 *)&vgainfo;
for(i=0; i<sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2); i+=4) for(i=0; i<sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2); i+=4)
@ -1111,6 +1151,147 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port)
/* step 2, TMDS, (only need if CMOS option is enabled) */ /* step 2, TMDS, (only need if CMOS option is enabled) */
if (cfg->gfx_tmds) { if (cfg->gfx_tmds) {
/**
* PCIe Initialization for DDI.
* The VBIOS/Driver is responsible for DDI programming sequence,
* The SBIOS is responsible for programming the lane and clock muxing specific to each case.
* Refer to RPR Chapter 7: "PCIe Initialization for DDI".
* Note: This programming must be done before hold training is released.
*/
switch (cfg->gfx_pcie_config) {
case 1: /* 1x16 GFX -default case, no programming required */
break;
case 2: /* 1x8 GFX on Lanes 0-7 */
case 5: /* 1x4 GPP on Lanes 0-3 */
set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 6, 0x1 << 6); /* Disables PCIe mode on PHY Lanes 8-11 */
set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 7, 0x1 << 7); /* Disables PCIe mode on PHY Lanes 12-15 */
break;
case 3: /* 1x8 on Lanes 8-15 */
case 7: /* 1x4 GPP on Lanes 8-11 */
/* TXCLK */
set_nbmisc_enable_bits(nb_dev, 0x07, 1 << 16, 1 << 16);
set_nbmisc_enable_bits(nb_dev, 0x07, 0xF << 12, 0xF << 12);
set_nbmisc_enable_bits(nb_dev, 0x07, 0x3 << 24, 0x2 << 24);
set_nbmisc_enable_bits(nb_dev, 0x28, 0x3 << 0, 0x0 << 0);
/* RXCLK */
set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 8, 0x2 << 8);
set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 10, 0x2 << 10);
set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 12, 0x2 << 12);
set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 14, 0x2 << 14);
/* TX Lane Muxing */
set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 2, 0x1 << 2);
set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 3, 0x1 << 3);
set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 4, 0x1 << 4);
set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 5, 0x1 << 5);
break;
case 4: /* 2x8 */
case 10: /* 1x4 GPP on Lanes 0-3 and 1x4 GPP on Lanes 8-11 */
case 14: /* 1x8 GFX on Lanes 0-7 and 1x4 GPP on Lanes 8-11 */
case 17: /* 1x4 GPP on Lanes 0-3 and 1x8 GFX on Lanes 8-15 */
/* Set dual slot configuration */
set_nbmisc_enable_bits(nb_dev, 0x08, 0xF << 8, 0x5 << 8);
break;
case 9: /* PCIe 2x4 GPPs on Lanes 0-7 */
case 6: /* PCIe 1x4 GPP on Lanes 4-7 */
/* Set dual slot configuration */
set_nbmisc_enable_bits(nb_dev, 0x08, 0xF << 8, 0x5 << 8);
/* TXCLK */
set_nbmisc_enable_bits(nb_dev, 0x07, 1 << 16, 0 << 16);
set_nbmisc_enable_bits(nb_dev, 0x07, 0xF << 12, 0x0 << 12);
set_nbmisc_enable_bits(nb_dev, 0x07, 0x3 << 20, 0x0 << 20);
set_nbmisc_enable_bits(nb_dev, 0x28, 0x1 << 0, 0x0 << 0);
/* RXCLK */
set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 8, 0x0 << 8);
set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 10, 0x1 << 10);
set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 12, 0x3 << 12);
set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 14, 0x0 << 14);
/* TX Lane Muxing */
set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 1, 0x1 << 1);
set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 6, 0x1 << 6);
set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 7, 0x1 << 7);
break;
case 13: /* 2x4 GPPs on Lanes 8-15 */
case 8: /* 1x4 GPP on Lanes 12-15 */
/* Set dual slot configuration */
set_nbmisc_enable_bits(nb_dev, 0x08, 0xF << 8, 0x5 << 8);
/* TXCLK */
set_nbmisc_enable_bits(nb_dev, 0x07, 1 << 16, 1 << 16);
set_nbmisc_enable_bits(nb_dev, 0x07, 0xF << 12, 0xF << 12);
set_nbmisc_enable_bits(nb_dev, 0x07, 0x3 << 24, 0x2 << 24);
set_nbmisc_enable_bits(nb_dev, 0x28, 0x3 << 0, 0x3 << 0);
/* RXCLK */
set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 8, 0x2 << 8);
set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 10, 0x3 << 10);
set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 12, 0x1 << 12);
set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 14, 0x2 << 14);
/* TX Lane Muxing */
set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 2, 0x1 << 2);
set_nbmisc_enable_bits(nb_dev, 0x28, 0x1 << 14, 0x1 << 14);
set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 4, 0x1 << 4);
set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 5, 0x1 << 5);
break;
case 15: /* 1x8 GFX on Lanes 0-7 and 1x4 GPP on Lanes 12-15 */
case 11: /* 1x4 GPP on Lanes 0-3 and 1x4 GPP on Lanes 12-15 */
/* Set dual slot configuration */
set_nbmisc_enable_bits(nb_dev, 0x08, 0xF << 8, 0x5 << 8);
/* TXCLK */
set_nbmisc_enable_bits(nb_dev, 0x07, 1 << 16, 0 << 16);
set_nbmisc_enable_bits(nb_dev, 0x07, 0xF << 12, 0x0 << 12);
set_nbmisc_enable_bits(nb_dev, 0x07, 0x3 << 20, 0x0 << 20);
set_nbmisc_enable_bits(nb_dev, 0x28, 0x3 << 0, 0x1 << 0);
/* RXCLK */
set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 8, 0x0 << 8);
set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 10, 0x0 << 10);
set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 12, 0x1 << 12);
set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 14, 0x3 << 14);
/* TX Lane Muxing */
set_nbmisc_enable_bits(nb_dev, 0x28, 0x1 << 14, 0x1 << 14);
set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 6, 0x1 << 6);
break;
case 16: /* 1x8 GFX on Lanes 8-15 and 1x4 GPP on Lanes 4-7 */
case 12: /* 1x4 GPP on Lanes 4-7 and 1x8 GFX on Lanes 8-15 */
/* Set dual slot configuration */
set_nbmisc_enable_bits(nb_dev, 0x08, 0xF << 8, 0x5 << 8);
/* TXCLK */
set_nbmisc_enable_bits(nb_dev, 0x07, 1 << 16, 1 << 16);
set_nbmisc_enable_bits(nb_dev, 0x07, 0xF << 12, 0xF << 12);
set_nbmisc_enable_bits(nb_dev, 0x07, 0x3 << 24, 0x2 << 24);
set_nbmisc_enable_bits(nb_dev, 0x07, 0x3 << 22, 0x2 << 22);
set_nbmisc_enable_bits(nb_dev, 0x28, 0x3 << 0, 0x2 << 0);
/* RXCLK */
set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 8, 0x2 << 8);
set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 10, 0x2 << 10);
set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 12, 0x3 << 12);
set_nbmisc_enable_bits(nb_dev, 0x27, 0x3 << 14, 0x1 << 14);
/* TX Lane Muxing */
set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 2, 0x1 << 2);
set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 3, 0x1 << 3);
set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 1, 0x1 << 1);
set_nbmisc_enable_bits(nb_dev, 0x27, 0x1 << 4, 0x1 << 4);
break;
default:
printk(BIOS_INFO, "Incorrect configuration of external GFX slot.\n");
break;
}
/* DDI Configuration */
switch (cfg->gfx_ddi_config) {
case 1: /* DDI_SL lanes0-3 */
nbmisc_write_index(nb_dev, 0x74, GFX_CONFIG_DDI);
break;
case 2: /* DDI_SL lanes4-7 */
nbmisc_write_index(nb_dev, 0x74, (GFX_CONFIG_DDI << 8));
break;
case 5: /* DDI_SL lanes0-4, lanes4-7 */
nbmisc_write_index(nb_dev, 0x74, (GFX_CONFIG_DDI << 8) | GFX_CONFIG_DDI);
break;
case 6: /* DDI_DL lanes0-7 */
nbmisc_write_index(nb_dev, 0x74, (GFX_CONFIG_DDI << 8) | GFX_CONFIG_DDI);
break;
default:
printk(BIOS_INFO, "Incorrect configuration of external GFX slot.\n");
break;
}
} }
#if 1 /* external clock mode */ #if 1 /* external clock mode */
@ -1123,8 +1304,6 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port)
/* 5.9.1.3 Selects the GFX REFCLK to be the source for PLL A. */ /* 5.9.1.3 Selects the GFX REFCLK to be the source for PLL A. */
/* 5.9.1.4 Selects the GFX REFCLK to be the source for PLL B. */ /* 5.9.1.4 Selects the GFX REFCLK to be the source for PLL B. */
/* 5.9.1.5 Selects the GFX REFCLK to be the source for PLL C. */ /* 5.9.1.5 Selects the GFX REFCLK to be the source for PLL C. */
set_nbmisc_enable_bits(nb_dev, 0x28, 3 << 6 | 3 << 8 | 3 << 10,
1 << 6 | 1 << 8 | 1 << 10);
reg32 = nbmisc_read_index(nb_dev, 0x28); reg32 = nbmisc_read_index(nb_dev, 0x28);
printk(BIOS_DEBUG, "misc 28 = %x\n", reg32); printk(BIOS_DEBUG, "misc 28 = %x\n", reg32);