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psp_verstage: convert relative address in EFS2 

Addresses in AMD fw table with EFS gen2 are relative addresses, but
PSP doesn't accept relative addresses in update_psp_bios_dir().

Check for EFS gen2 and convert them as needed.

BUG=b:194263115
TEST=build and boot on guybrush and shuboz

Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I95813beba7278480e6640599fcf7445923259361
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58316
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Kangheui Won 2021-10-18 15:35:28 +11:00 committed by Patrick Georgi
parent cb3745c407
commit fab6e44a95
4 changed files with 13 additions and 4 deletions
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4
src/soc/amd/cezanne/include/soc/iomap.h
View File

@ -36,10 +36,10 @@
#define APU_EMMC_BASE 0xfedd5000 #define APU_EMMC_BASE 0xfedd5000
#define APU_EMMC_CONFIG_BASE 0xfedd5800 #define APU_EMMC_CONFIG_BASE 0xfedd5800
#define FLASH_BASE_ADDR ((0xffffffff - CONFIG_ROM_SIZE) + 1)
#endif /* ENV_X86 */ #endif /* ENV_X86 */
#define FLASH_BASE_ADDR ((0xffffffff - CONFIG_ROM_SIZE) + 1)
/* I/O Ranges */ /* I/O Ranges */
#define ACPI_IO_BASE 0x0400 #define ACPI_IO_BASE 0x0400
#define ACPI_PM_EVT_BLK (ACPI_IO_BASE + 0x00) #define ACPI_PM_EVT_BLK (ACPI_IO_BASE + 0x00)

2
src/soc/amd/common/block/include/amdblocks/psp_efs.h
View File

@ -29,6 +29,8 @@ struct second_gen_efs { /* todo: expand for Server products */
uint32_t reserved:31; uint32_t reserved:31;
} __attribute__((packed)); } __attribute__((packed));
#define EFS_SECOND_GEN 0
/* Copied from coreboot/util/amdfwtool.h */ /* Copied from coreboot/util/amdfwtool.h */
struct embedded_firmware { struct embedded_firmware {
uint32_t signature; /* 0x55aa55aa */ uint32_t signature; /* 0x55aa55aa */

7
src/soc/amd/common/psp_verstage/psp_verstage.c
View File

@ -10,6 +10,7 @@
#include <console/console.h> #include <console/console.h>
#include <fmap.h> #include <fmap.h>
#include <pc80/mc146818rtc.h> #include <pc80/mc146818rtc.h>
#include <soc/iomap.h>
#include <soc/psp_transfer.h> #include <soc/psp_transfer.h>
#include <security/vboot/vbnv.h> #include <security/vboot/vbnv.h>
#include <security/vboot/misc.h> #include <security/vboot/misc.h>
@ -121,6 +122,12 @@ static uint32_t update_boot_region(struct vb2_context *ctx)
return POSTCODE_BDT1_COOKIE_MISMATCH_ERROR; return POSTCODE_BDT1_COOKIE_MISMATCH_ERROR;
} }
/* EFS2 uses relative address and PSP isn't happy with that */
if (ef_table->efs_gen.gen == EFS_SECOND_GEN) {
psp_dir_addr = FLASH_BASE_ADDR + (psp_dir_addr & SPI_ADDR_MASK);
bios_dir_addr = FLASH_BASE_ADDR + (bios_dir_addr & SPI_ADDR_MASK);
}
if (update_psp_bios_dir(&psp_dir_addr, &bios_dir_addr)) { if (update_psp_bios_dir(&psp_dir_addr, &bios_dir_addr)) {
printk(BIOS_ERR, "Error: Updated BIOS Directory could not be set.\n"); printk(BIOS_ERR, "Error: Updated BIOS Directory could not be set.\n");
return POSTCODE_UPDATE_PSP_BIOS_DIR_ERROR; return POSTCODE_UPDATE_PSP_BIOS_DIR_ERROR;

4
src/soc/amd/picasso/include/soc/iomap.h
View File

@ -61,10 +61,10 @@
#define APU_EMMC_BASE 0xfedd5000 #define APU_EMMC_BASE 0xfedd5000
#define APU_EMMC_CONFIG_BASE 0xfedd5800 #define APU_EMMC_CONFIG_BASE 0xfedd5800
#define FLASH_BASE_ADDR ((0xffffffff - CONFIG_ROM_SIZE) + 1)
#endif /* ENV_X86 */ #endif /* ENV_X86 */
#define FLASH_BASE_ADDR ((0xffffffff - CONFIG_ROM_SIZE) + 1)
/* I/O Ranges */ /* I/O Ranges */
#define ACPI_IO_BASE 0x400 #define ACPI_IO_BASE 0x400
#define ACPI_PM_EVT_BLK (ACPI_IO_BASE + 0x00) /* 4 bytes */ #define ACPI_PM_EVT_BLK (ACPI_IO_BASE + 0x00) /* 4 bytes */