GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mainboard/hp/dl145_g1: Fix coding style 

Change-Id: I8cfddbf49b3042d46956985425990360f0903b1f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/23531
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Elyes HAOUAS 2018-02-01 09:04:09 +01:00 committed by Patrick Georgi
parent d3c0c0c318
commit fabd0f4fa8
2 changed files with 11 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

23
src/mainboard/hp/dl145_g1/get_bus_conf.c
View File

@ -52,7 +52,8 @@ void get_bus_conf(void)
device_t dev;
int i;
if(get_bus_conf_done == 1) return; //do it only once
if (get_bus_conf_done == 1)
return; //do it only once
get_bus_conf_done = 1;
@ -60,7 +61,7 @@ void get_bus_conf(void)
struct mb_sysconf_t *m = sysconf.mb;
sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
for(i = 0; i < sysconf.hc_possible_num; i++) {
for (i = 0; i < sysconf.hc_possible_num; i++) {
sysconf.pci1234[i] = pci1234x[i];
sysconf.hcdn[i] = hcdnx[i];
}
@ -75,30 +76,24 @@ void get_bus_conf(void)
/* 8111 */
dev = dev_find_slot(m->bus_8111_0, PCI_DEVFN(sysconf.sbdn,0));
if (dev) {
if (dev)
m->bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
else {
else
printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:03.0, using defaults\n", m->bus_8111_0);
}
/* 8131-1 */
dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN(m->sbdn3,0));
if (dev) {
if (dev)
m->bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
else {
else
printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:01.0, using defaults\n", m->bus_8131_0);
}
/* 8131-2 */
dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN(m->sbdn3+1,0));
if (dev) {
if (dev)
m->bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
else {
else
printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:02.0, using defaults\n", m->bus_8131_0);
}
/*I/O APICs: APIC ID Version State Address*/

6
src/mainboard/hp/dl145_g1/romstage.c
View File

@ -175,12 +175,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
enable_smbus();
int i;
for(i = 0; i < 2; i++) {
for (i = 0; i < 2; i++)
activate_spd_rom(&sysinfo->ctrl[i]);
}
for(i = RC0; i <= RC1; i<<=1) {
for (i = RC0; i <= RC1; i <<= 1)
change_i2c_mux(i);
}
//dump_spd_registers(&sysinfo->ctrl[0]);
//dump_spd_registers(&sysinfo->ctrl[1]);