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mb/google/var/banshee: Add gpios to lock 

Variant should honor locked gpios from baseboard, but not the last.
Variant can add more gpios to lock if needed.

BUG=b:216583542
TEST='emerge-brya coreboot chromeos-bootimage'

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Id5a2136e57e842fbd0b2c2836833106e7344afee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Eric Lai 2022-02-07 15:10:35 +08:00 committed by Felix Held
parent 85ec4e2a74
commit facdd7e04c
1 changed files with 29 additions and 29 deletions
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58
src/mainboard/google/brya/variants/banshee/gpio.c
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@ -45,12 +45,12 @@ static const struct pad_config override_gpio_table[] = {
/* B1 : SOC_VID1 */
/* B2 : VRALERT# ==> M2_SSD_PLA_L */
/* B3 : PROC_GP2 ==> NC */
PAD_NC(GPP_B3, NONE),
PAD_NC_LOCK(GPP_B3, NONE, LOCK_CONFIG),
/* B4 : PROC_GP3 ==> SSD_PERST_L */
/* B5 : ISH_I2C0_SDA ==> NC */
PAD_NC(GPP_B5, NONE),
PAD_NC_LOCK(GPP_B5, NONE, LOCK_CONFIG),
/* B6 : ISH_I2C0_SCL ==> NC */
PAD_NC(GPP_B6, NONE),
PAD_NC_LOCK(GPP_B6, NONE, LOCK_CONFIG),
/* B9 : NC */
/* B10 : NC */
/* B11 : PMCALERT# ==> EN_PP3300_WLAN */
@ -58,7 +58,7 @@ static const struct pad_config override_gpio_table[] = {
/* B13 : PLTRST# ==> PLT_RST_L */
/* B14 : SPKR ==> GPP_B14_STRAP */
/* B15 : TIME_SYNC0 ==> NC */
PAD_NC(GPP_B15, NONE),
PAD_NC_LOCK(GPP_B15, NONE, LOCK_CONFIG),
/* B16 : I2C5_SDA ==> PCH_I2C_TCHPAD_SDA */
/* B17 : I2C5_SCL ==> PCH_I2C_TCHPAD_SCL */
/* B18 : ADR_COMPLETE ==> GPP_B18_STRAP */
@ -82,13 +82,13 @@ static const struct pad_config override_gpio_table[] = {
/* C7 : SML1DATA ==> USI_INT */
/* D0 : ISH_GP0 ==> NC */
PAD_NC(GPP_D0, NONE),
PAD_NC_LOCK(GPP_D0, NONE, LOCK_CONFIG),
/* D1 : ISH_GP1 ==> NC */
PAD_NC(GPP_D1, NONE),
PAD_NC_LOCK(GPP_D1, NONE, LOCK_CONFIG),
/* D2 : ISH_GP2 ==> NC */
PAD_NC(GPP_D2, NONE),
PAD_NC_LOCK(GPP_D2, NONE, LOCK_CONFIG),
/* D3 : ISH_GP3 ==> NC */
PAD_NC(GPP_D3, NONE),
PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG),
/* D4 : IMGCLKOUT0 ==> BT_DISABLE_L */
/* D5 : SRCCLKREQ0# ==> SSD_CLKREQ_ODL */
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
@ -100,28 +100,28 @@ static const struct pad_config override_gpio_table[] = {
/* D9 : ISH_SPI_CS# ==> USB_C2_LSX_TX */
/* D10 : ISH_SPI_CLK ==> USB_C2_LSX_RX_STRAP */
/* D11 : ISH_SPI_MISO ==> USB_C3_LSX_TX */
PAD_CFG_NF(GPP_D11, NONE, DEEP, NF4),
PAD_CFG_NF_LOCK(GPP_D11, NONE, NF4, LOCK_CONFIG),
/* D12 : ISH_SPI_MOSI ==> GPP_D12_STRAP */
/* D13 : ISH_UART0_RXD ==> NC */
PAD_NC(GPP_D13, NONE),
PAD_NC_LOCK(GPP_D13, NONE, LOCK_CONFIG),
/* D14 : ISH_UART0_TXD ==> NC */
PAD_NC(GPP_D14, NONE),
PAD_NC_LOCK(GPP_D14, NONE, LOCK_CONFIG),
/* D15 : ISH_UART0_RTS# ==> NC */
PAD_NC(GPP_D15, NONE),
PAD_NC_LOCK(GPP_D15, NONE, LOCK_CONFIG),
/* D16 : ISH_UART0_CTS# ==> NC */
PAD_NC(GPP_D16, NONE),
PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG),
/* D17 : UART1_RXD ==> NC */
PAD_NC(GPP_D17, NONE),
PAD_NC_LOCK(GPP_D17, NONE, LOCK_CONFIG),
/* D18 : UART1_TXD ==> USI_RST_L */
PAD_CFG_GPO(GPP_D18, 0, DEEP),
PAD_CFG_GPO_LOCK(GPP_D18, 0, LOCK_CONFIG),
/* D19 : I2S_MCLK1_OUT ==> I2S_MCLK_R */
/* E0 : SATAXPCIE0 ==> NC */
PAD_NC(GPP_E0, NONE),
/* E1 : THC0_SPI1_IO2 ==> NC */
PAD_NC(GPP_E1, NONE),
PAD_NC_LOCK(GPP_E1, NONE, LOCK_CONFIG),
/* E2 : THC0_SPI1_IO3 ==> NC */
PAD_NC(GPP_E2, NONE),
PAD_NC_LOCK(GPP_E2, NONE, LOCK_CONFIG),
/* E3 : PROC_GP0 ==> NC */
PAD_NC(GPP_E3, NONE),
/* E4 : SATA_DEVSLP0 ==> USB4_BB_RT_FORCE_PWR */
@ -133,19 +133,19 @@ static const struct pad_config override_gpio_table[] = {
/* E8 : SLP_DRAM# ==> WIFI_DISABLE_L */
/* E9 : USB_OC0# ==> USB_C0_OC_ODL */
/* E10 : THC0_SPI1_CS# ==> NC */
PAD_NC(GPP_E10, NONE),
PAD_NC_LOCK(GPP_E10, NONE, LOCK_CONFIG),
/* E11 : THC0_SPI1_CLK ==> NC */
PAD_NC(GPP_E11, NONE),
PAD_NC_LOCK(GPP_E11, NONE, LOCK_CONFIG),
/* E12 : THC0_SPI1_IO1 ==> NC */
PAD_NC(GPP_E12, NONE),
PAD_NC_LOCK(GPP_E12, NONE, LOCK_CONFIG),
/* E13 : THC0_SPI1_IO2 ==> NC */
PAD_NC(GPP_E13, NONE),
PAD_NC_LOCK(GPP_E13, NONE, LOCK_CONFIG),
/* E14 : DDSP_HPDA ==> SOC_EDP_HPD */
/* E15 : RSVD_TP ==> PCH_WP_OD */
/* E16 : RSVD_TP ==> NC */
PAD_NC(GPP_E16, NONE),
/* E17 : THC0_SPI1_INT# ==> NC */
PAD_NC(GPP_E17, NONE),
PAD_NC_LOCK(GPP_E17, NONE, LOCK_CONFIG),
/* E18 : DDP1_CTRLCLK ==> USB_C0_LSX_SOC_TX */
/* E19 : DDP1_CTRLDATA ==> USB0_C0_LSX_SOC_RX_STRAP */
/* E20 : DDP2_CTRLCLK ==> USB_C1_LSX_SOC_TX */
@ -168,16 +168,16 @@ static const struct pad_config override_gpio_table[] = {
/* F9 : BOOTMPC ==> SLP_S0_GATE_R */
/* F10 : GPPF10_STRAP */
/* F11 : THC1_SPI2_CLK ==> NC */
PAD_NC(GPP_F11, NONE),
PAD_NC_LOCK(GPP_F11, NONE, LOCK_CONFIG),
/* F12 : GSXDOUT ==> NC */
PAD_NC(GPP_F12, NONE),
PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG),
/* F13 : GSXDOUT ==> NC */
PAD_NC(GPP_F13, NONE),
PAD_NC_LOCK(GPP_F13, NONE, LOCK_CONFIG),
/* F14 : GSXDIN ==> TCHPAD_INT_ODL */
/* F15 : GSXSRESET# ==> NC */
PAD_NC(GPP_F15, NONE),
PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG),
/* F16 : GSXCLK ==> NC */
PAD_NC(GPP_F16, NONE),
PAD_NC_LOCK(GPP_F16, NONE, LOCK_CONFIG),
/* F17 : THC1_SPI2_RST# ==> EC_PCH_INT_ODL */
/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
/* F19 : SRCCLKREQ6# ==> NC */
@ -205,9 +205,9 @@ static const struct pad_config override_gpio_table[] = {
PAD_NC(GPP_H9, NONE),
/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
/* H12 : I2C7_SDA ==> NC */
PAD_NC(GPP_H12, NONE),
PAD_NC_LOCK(GPP_H12, NONE, LOCK_CONFIG),
/* H13 : I2C7_SCL ==> EN_PP3300_TCHSCR */
PAD_CFG_GPO(GPP_H13, 1, DEEP),
PAD_CFG_GPO_LOCK(GPP_H13, 1, LOCK_CONFIG),
/* H14 : NC */
/* H15 : DDPB_CTRLCLK ==> NC */
PAD_NC(GPP_H15, NONE),