superio/nuvoton/nct5539d: Add nuvoton NCT5539D specific superio.asl
This port is based on NCT6776 Change-Id: Ib8d64e8faa74802ab0213d87881e57d4d9bd1c35 Signed-off-by: Pavel Sayekat <pavelsayekat@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35028 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Pavel Sayekat
Felix Held
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Christoph Grenz <christophg+cb@grenz-bonn.de>
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* Copyright (C) 2013, 2016 secunet Security Networks AG
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* Copyright (C) 2017 Tobias Diedrich <ranma+coreboot@tdiedrich.de>
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* Copyright (C) 2019 Pavel Sayekat <pavelsayekat@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/*
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* Include this file into a mainboard's DSDT _SB device tree and it will
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* expose the NCT5539D SuperIO and some of its functionality.
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*
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* It allows the change of IO ports, IRQs and DMA settings on logical
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* devices, disabling and reenabling logical devices.
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*
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* LDN State
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* 0x2 SP1 Implemented, untested
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* 0x5 KBC Implemented, untested
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* 0x8 GPIO Implemented, untested
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* 0xb HWM Implemented, untested
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*
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* Controllable through preprocessor defines:
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* SUPERIO_DEV Device identifier for this SIO (e.g. SIO0)
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* SUPERIO_PNP_BASE I/O address of the first PnP configuration register
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* NCT5539D_SHOW_SP1 If defined, Serial Port 1 will be exposed.
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* NCT5539D_SHOW_KBC If defined, the Keyboard Controller will be exposed.
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* NCT5539D_SHOW_GPIO If defined, GPIO support will be exposed.
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* NCT5539D_SHOW_HWM If defined, the Environment Controller will be exposed.
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*/
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#undef SUPERIO_CHIP_NAME
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#define SUPERIO_CHIP_NAME NCT5539D
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#include <superio/acpi/pnp.asl>
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#undef PNP_DEFAULT_PSC
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#define PNP_DEFAULT_PSC Return (0) /* no power management */
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Device(SUPERIO_DEV) {
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Name (_HID, EisaId("PNP0A05"))
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Name (_STR, Unicode("Nuvoton NCT5539D Super I/O"))
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Name (_UID, SUPERIO_UID(SUPERIO_DEV,))
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/* SuperIO configuration ports */
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OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 0x02)
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Field (CREG, ByteAcc, NoLock, Preserve)
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{
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PNP_ADDR_REG, 8,
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PNP_DATA_REG, 8,
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}
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IndexField (ADDR, DATA, ByteAcc, NoLock, Preserve)
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{
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Offset (0x07),
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PNP_LOGICAL_DEVICE, 8, /* Logical device selector */
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Offset (0x30),
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PNP_DEVICE_ACTIVE, 1, /* Logical device activation */
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ACT1, 1, /* Logical device activation */
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ACT2, 1, /* Logical device activation */
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ACT3, 1, /* Logical device activation */
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ACT4, 1, /* Logical device activation */
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ACT5, 1, /* Logical device activation */
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ACT6, 1, /* Logical device activation */
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ACT7, 1, /* Logical device activation */
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Offset (0x60),
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PNP_IO0_HIGH_BYTE, 8, /* First I/O port base - high byte */
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PNP_IO0_LOW_BYTE, 8, /* First I/O port base - low byte */
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Offset (0x62),
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PNP_IO1_HIGH_BYTE, 8, /* Second I/O port base - high byte */
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PNP_IO1_LOW_BYTE, 8, /* Second I/O port base - low byte */
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Offset (0x64),
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PNP_IO2_HIGH_BYTE, 8, /* Third I/O port base - high byte */
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PNP_IO2_LOW_BYTE, 8, /* Third I/O port base - low byte */
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Offset (0x70),
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PNP_IRQ0, 8, /* First IRQ */
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Offset (0x72),
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PNP_IRQ1, 8, /* Second IRQ */
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Offset (0x74),
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PNP_DMA0, 8, /* DRQ */
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}
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Method (_CRS)
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{
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/* Announce the used I/O ports to the OS */
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Return (ResourceTemplate () {
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IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE, 0x01, 0x02)
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})
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}
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#undef PNP_ENTER_MAGIC_1ST
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#undef PNP_ENTER_MAGIC_2ND
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#undef PNP_ENTER_MAGIC_3RD
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#undef PNP_ENTER_MAGIC_4TH
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#undef PNP_EXIT_MAGIC_1ST
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#undef PNP_EXIT_SPECIAL_REG
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#undef PNP_EXIT_SPECIAL_VAL
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#define PNP_ENTER_MAGIC_1ST 0x87
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#define PNP_ENTER_MAGIC_2ND 0x87
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#define PNP_EXIT_MAGIC_1ST 0xaa
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#include <superio/acpi/pnp_config.asl>
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#ifdef NCT5539D_SHOW_SP1
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#undef SUPERIO_UART_LDN
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#undef SUPERIO_UART_DDN
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#undef SUPERIO_UART_PM_REG
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#undef SUPERIO_UART_PM_VAL
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#undef SUPERIO_UART_PM_LDN
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#define SUPERIO_UART_LDN 2
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#include <superio/acpi/pnp_uart.asl>
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#endif
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#ifdef NCT5539D_SHOW_KBC
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#undef SUPERIO_KBC_LDN
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#undef SUPERIO_KBC_PS2M
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#undef SUPERIO_KBC_PS2LDN
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#define SUPERIO_KBC_LDN 5
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#define SUPERIO_KBC_PS2M
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#include <superio/acpi/pnp_kbc.asl>
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#endif
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#ifdef NCT5539D_SHOW_HWM
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#undef SUPERIO_PNP_HID
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#undef SUPERIO_PNP_LDN
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#undef SUPERIO_PNP_DDN
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#undef SUPERIO_PNP_PM_REG
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#undef SUPERIO_PNP_PM_VAL
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#undef SUPERIO_PNP_PM_LDN
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#undef SUPERIO_PNP_IO0
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#undef SUPERIO_PNP_IO1
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#undef SUPERIO_PNP_IO2
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#undef SUPERIO_PNP_IRQ0
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#undef SUPERIO_PNP_IRQ1
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#undef SUPERIO_PNP_DMA
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#define SUPERIO_PNP_LDN 11
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#define SUPERIO_PNP_IO0 0x08, 0x08
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#define SUPERIO_PNP_IO1 0x08, 0x08
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#define SUPERIO_PNP_IRQ0
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#include <superio/acpi/pnp_generic.asl>
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#endif
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#ifdef NCT5539D_SHOW_GPIO
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#undef SUPERIO_PNP_HID
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#undef SUPERIO_PNP_LDN
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#undef SUPERIO_PNP_DDN
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#undef SUPERIO_PNP_PM_REG
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#undef SUPERIO_PNP_PM_VAL
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#undef SUPERIO_PNP_PM_LDN
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#undef SUPERIO_PNP_IO0
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#undef SUPERIO_PNP_IO1
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#undef SUPERIO_PNP_IO2
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#undef SUPERIO_PNP_IRQ0
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#undef SUPERIO_PNP_IRQ1
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#undef SUPERIO_PNP_DMA
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#undef PNP_DEVICE_ACTIVE
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#define PNP_DEVICE_ACTIVE ACT3
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#define SUPERIO_PNP_LDN 8
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#define SUPERIO_PNP_IO0 0x08, 0x08
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#include <superio/acpi/pnp_generic.asl>
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#endif
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}
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