soc/intel/skylake: Enable XHCI clock gate control in ACPI
Enable SS link trunk clock gating & D3hot when device enters D3 state. Similarly disable SS link trunk clock gating & D3hot when device enters D0 state TEST=Build & boot Poppy board. Check working for XHCI wake when DUT is in S3. Change-Id: Ida2afa2e5f9404c0c15d7027480a28a003ad9a40 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/18879 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -93,12 +93,18 @@ Device (XHCI)
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Offset (0x10),
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, 16,
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XMEM, 16, /* MEM_BASE */
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Offset (0x50), /* XHCLKGTEN */
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, 2,
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STGE, 1, /* SS Link Trunk clock gating enable */
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Offset (0x74),
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D0D3, 2, /* POWERSTATE */
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, 6,
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PMEE, 1, /* PME_EN */
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, 6,
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PMES, 1, /* PME_STS */
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Offset (0xA2),
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, 2,
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D3HE, 1, /* D3_hot_en */
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}
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OperationRegion (XREG, SystemMemory,
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@ -124,6 +130,10 @@ Device (XHCI)
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Return
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}
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/* Disable d3hot and SS link trunk clock gating */
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Store(Zero, ^D3HE)
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Store(Zero, ^STGE)
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/* If device is in D3, set back to D0 */
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If (LEqual (^D0D3, 3)) {
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Store (Zero, Local0)
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@ -178,6 +188,10 @@ Device (XHCI)
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/* Enable USB2 PHY SUS Well Power Gating in D0/D0i2/D0i3/D3 */
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Store (3, ^UPSW)
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/* Enable d3hot and SS link trunk clock gating */
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Store(One, ^D3HE)
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Store(One, ^STGE)
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/* Now put device in D3 */
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Store (3, Local0)
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Store (Local0, ^D0D3)
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