disable watchdog, and it goes much better!
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2200 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -43,7 +43,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
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#include "sdram/generic_sdram.c"
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#define PLLMSRhi 0x00000226
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#define PLLMSRlo 0x81000048
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#define PLLMSRlo 0x00000008
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#define PLLMSRlo1 ((0xde << 16) | (1 << 26) | (1 << 24))
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#define PLLMSRlo2 ((1<<14) |(1<<13) | (1<<0))
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#include "northbridge/amd/gx2/pll_reset.c"
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@ -80,6 +80,7 @@ static void main(unsigned long bist)
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static const struct mem_controller memctrl [] = {
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{.channel0 = {(0xa<<3)|0, (0xa<<3)|1}}
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};
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unsigned char temp;
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msr_init();
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@ -97,7 +98,38 @@ static void main(unsigned long bist)
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sdram_initialize(1, memctrl);
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print_err("Done sdram_initialize\n");
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print_err("Disable watchdog\n");
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outb( 0x87, 0x4E); //enter SuperIO configuration mode
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outb( 0x87, 0x4E);
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outb(0x20, 0x4e);
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temp = inb(0x4f);
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print_debug_hex8(temp);
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if (temp != 0x52){
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print_err("CAN NOT READ SUPERIO VID\n");
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}
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outb(0x29, 0x4e);
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outb(0x7c, 0x4f);
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outb( 0x07, 0x4E); //enable logical device 9
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outb( 0x09, 0x4F);
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outb(0x30, 0x4e);
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outb(1, 0x4f);
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outb( 0xF0, 0x4E); //set GP33 as outbut in configuration register F0h Bit4 = \u20180\u2019
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outb( 0xC7, 0x4F);
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outb( 0xF1, 0x4E); //clr GP33 (Bit4) value in cofiguration register F1h to \u20181\u2019 disables
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temp = inb(0x4F); //watchdog function. Make sure to let the other Bits unchanged!
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print_debug_hex8(temp);print_debug(":");
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temp = temp & ~8;
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outb( temp, 0x4F);
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temp = inb(0x4F); //watchdog function. Make sure to let the other Bits unchanged!
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print_debug_hex8(temp);print_debug("\n");
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/* Check all of memory */
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// ram_check(0, 16384);
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ram_check(0x20000, 0x24000);
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print_err("Let's go loopy\n");
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ram_check(0x00000000, 640*1024);
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}
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