Snow bootblock (bloated/debug version)

This is the bloated Snow bootblock which includes:
- SPI driver
- UART, including requisite I2C, Maxim PMIC, and clock config code.
- Adjustments for magic offsets (id section, stack pointer address)

This is just a temporary solution until we have romstage loading.
Once that happens, we'll rip out all but the code necessary for
copying SPI ROM content into SRAM.

Change-Id: I2a11e272eb9b6f626b5d9783eabb4a720a1d06be
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2170
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
David Hendricks 2013-01-17 15:07:35 -08:00 committed by Ronald G. Minnich
parent 1c706dc858
commit fba42a793a
8 changed files with 2173 additions and 14 deletions

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@ -259,7 +259,7 @@ $(objcbfs)/bootblock.debug: $(objgenerated)/bootblock.o $(objgenerated)/bootbloc
ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y)
$(LD) -m armelf_linux_eabi -static -o $@.tmp -L$(obj) $< -T $(objgenerated)/bootblock.ld $(LD) -m armelf_linux_eabi -static -o $@.tmp -L$(obj) $< -T $(objgenerated)/bootblock.ld
else else
$(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/bootblock.ld $< $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/bootblock.ld -Wl,--start-group $< $(LIBGCC_FILE_NAME) -Wl,--end-group
endif endif
################################################################################ ################################################################################

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@ -40,6 +40,7 @@ void main(unsigned long bist)
if (boot_cpu()) { if (boot_cpu()) {
bootblock_mainboard_init(); bootblock_mainboard_init();
bootblock_cpu_init();
} }
entry = findstage(target1); entry = findstage(target1);

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@ -1,6 +1,6 @@
SECTIONS { SECTIONS {
/* FIXME: determine a sensible location... */ /* FIXME: determine a sensible location... */
. = (0x2024000) - (__id_end - __id_start); . = (0x2026400);
.id (.): { .id (.): {
*(.id) *(.id)
} }

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@ -35,11 +35,11 @@
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm) OUTPUT_ARCH(arm)
ENTRY(_start) /* ENTRY(_start) */
SECTIONS SECTIONS
{ {
. = CONFIG_ROMSTAGE_BASE; . = 0x02023400 + 0x4000;
.romtext . : { .romtext . : {
_rom = .; _rom = .;

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@ -45,7 +45,7 @@ config IRAM_TOP
config SYS_INIT_SP_ADDR config SYS_INIT_SP_ADDR
hex hex
default 0x0204F800 default 0x02058000
config IRAM_STACK config IRAM_STACK
hex hex

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@ -17,16 +17,24 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/ */
#if 0
/*
* Set/clear program flow prediction and return the previous state.
*/
static int config_branch_prediction(int set_cr_z)
{
unsigned int cr;
/* System Control Register: 11th bit Z Branch prediction enable */
cr = get_cr();
set_cr(set_cr_z ? cr | CR_Z : cr & ~CR_Z);
return cr & CR_Z;
}
#endif
void bootblock_cpu_init(void); void bootblock_cpu_init(void);
void bootblock_cpu_init(void) void bootblock_cpu_init(void)
{ {
/* /* FIXME: this is a stub for now */
* FIXME: this is a stub for now. It should eventually copy
* romstage data (and maybe more) from SPI to SRAM.
*/
#if 0
volatile unsigned long *addr = (unsigned long *)0x1004330c;
*addr |= 0x100;
while (1) ;
#endif
} }

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@ -56,6 +56,10 @@ config MAINBOARD_VENDOR
string string
default "Samsung" default "Samsung"
config BOOTBLOCK_MAINBOARD_INIT
string
default "mainboard/google/snow/bootblock.c"
# SPL (second-phase loader) stuff # SPL (second-phase loader) stuff
config SPL_TEXT_BASE config SPL_TEXT_BASE
hex hex

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