mb/via/epia-m850: Drop support
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: Id6aa669542bcfd774fa5571d790f59f156a39a4b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36949 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Arthur Heymans
Kyösti Mälkki
parent
43d2527203
commit
fbc59ffb64
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@ -1,16 +0,0 @@
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if VENDOR_VIA
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choice
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prompt "Mainboard model"
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source "src/mainboard/via/*/Kconfig.name"
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endchoice
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source "src/mainboard/via/*/Kconfig"
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config MAINBOARD_VENDOR
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string
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default "VIA"
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endif # VENDOR_VIA
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@ -1,2 +0,0 @@
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config VENDOR_VIA
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bool "VIA"
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@ -1,45 +0,0 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2011-2012 Alexandru Gagniuc <mr.nuke.me@gmail.com>
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##
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## This program is free software: you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation, either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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if BOARD_VIA_EPIA_M850
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select CPU_VIA_NANO
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select NORTHBRIDGE_VIA_VX900
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select SUPERIO_FINTEK_F81865F
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select HAVE_PIRQ_TABLE
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select PIRQ_ROUTE
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select HAVE_MP_TABLE
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#select HAVE_OPTION_TABLE
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#select HAVE_ACPI_TABLES
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#select HAVE_ACPI_RESUME
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#select BOARD_HAS_FADT
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select BOARD_ROMSIZE_KB_512
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config MAINBOARD_DIR
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string
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default via/epia-m850
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config MAINBOARD_PART_NUMBER
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string
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default "EPIA-M850"
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config IRQ_SLOT_COUNT
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int
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default 13
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endif # BOARD_VIA_EPIA_M850
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@ -1,2 +0,0 @@
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config BOARD_VIA_EPIA_M850
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bool "EPIA-M850"
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@ -1,7 +0,0 @@
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Category: mini
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Board URL: http://www.viaembedded.com/en/products/boards/1290/1/EPIA-M850.html
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ROM package: SOIC8
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ROM protocol: SPI
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ROM socketed: n
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Flashrom support: y
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Release year: 2010
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@ -1,108 +0,0 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2011-2013 Alexandru Gagniuc <mr.nuke.me@gmail.com>
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##
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## This program is free software: you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation, either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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chip northbridge/via/vx900 # Northbridge
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register "assign_pex_to_dp" = "0"
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register "pcie_port1_2_lane_wide" = "1"
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register "ext_int_route_to_pirq" = "'H'"
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device cpu_cluster 0 on # APIC cluster
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chip cpu/via/nano # VIA NANO
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device lapic 0 on end # APIC
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end
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end
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device domain 0 on
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device pci 0.0 on end # [0410] Host controller
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device pci 0.1 on end # [1410] Error Reporting
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device pci 0.2 on end # [2410] CPU Bus Control
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device pci 0.3 on end # [3410] DRAM Bus Control
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device pci 0.4 on end # [4410] Power Management
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device pci 0.5 on # [5410] APIC+Traffic Control
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chip drivers/generic/ioapic
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register "have_isa_interrupts" = "0"
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register "irq_on_fsb" = "1"
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register "enable_virtual_wire" = "1"
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register "base" = "(void *)0xfecc0000"
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device ioapic 2 on end
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end
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end
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device pci 0.6 off end # [6410] Scratch Registers
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device pci 0.7 on end # [7410] V4 Link Control
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device pci 1.0 on # [7122] VGA Chrome9 HD
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ioapic_irq 2 INTA 0x28
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end
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device pci 1.1 on # [9170] Audio Device
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ioapic_irq 2 INTA 0x29
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end
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device pci 3.0 on end # [a410] PEX1
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device pci 3.1 on end # [b410] PEX2
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device pci 3.2 on end # [c410] PEX3
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device pci 3.3 on end # [d410] PEX4
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device pci 3.4 on end # [e410] PCIE bridge
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device pci b.0 on end # [a409] USB Device
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device pci c.0 off end # [95d0] SDIO Host Controller
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device pci d.0 off end # [9530] Memory Card controller
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device pci f.0 on # [9001] SATA Controller
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ioapic_irq 1 INTA 0x15
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end
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device pci 10.0 on end # [3038] USB 1.1
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device pci 10.1 on end # [3038] USB 1.1
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device pci 10.2 on end # [3038] USB 1.1
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device pci 10.3 on end # [3038] USB 1.1
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device pci 10.4 on end # [3104] USB 2.0
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device pci 11.0 on # [8410] LPC Bus Control
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chip drivers/generic/ioapic
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register "have_isa_interrupts" = "1"
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register "irq_on_fsb" = "1"
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register "enable_virtual_wire" = "1"
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register "base" = "(void *)0xfec00000"
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device ioapic 1 on end
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end
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#chip drivers/generic/generic # DIMM 0 channel 1
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# device i2c 50 on end
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#end
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#chip drivers/generic/generic # DIMM 1 channel 1
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# device i2c 51 on end
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#end
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chip superio/fintek/f81865f # Super duper IO
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device pnp 4e.0 off end # Floppy
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device pnp 4e.3 off end # Parallel Port
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device pnp 4e.4 off end # Hardware Monitor
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device pnp 4e.5 off end # Keyboard not here
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device pnp 4e.6 off end # GPIO
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device pnp 4e.a off end # PME
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device pnp 4e.10 on # COM1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 4e.11 on # COM2
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 4e.12 on # COM3
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io 0x60 = 0x3e8
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irq 0x70 = 10
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end
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device pnp 4e.13 on # COM4
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io 0x60 = 0x2e8
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irq 0x70 = 11
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end
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end # superio/fintek/f81865f
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end # LPC
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device pci 11.7 on end # [a353] North-South control
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device pci 14.0 on end # [3288] Azalia HDAC
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end
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end
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@ -1,71 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me@gmail.com>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/pirq_routing.h>
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#include <device/pci_ids.h>
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#include <string.h> /* <- For memset */
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#define _OFF 0x00
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#define ___OFF 0x0000
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#define LNKA 1
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#define LNKB 2
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#define LNKC 3
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#define LNKD 4
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#define LNKE 5
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#define LNKF 6
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#define LNKG 7
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#define LNKH 8
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#define BITMAP 0xdce0
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/* The link that carries the SATA interrupt has its own mask, just in case
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* we want to make sure our SATA controller gets mapped to IRQ 14 */
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#define B_SATA BITMAP
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const struct irq_routing_table intel_irq_routing_table = {
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PIRQ_SIGNATURE, /* u32 signature */
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PIRQ_VERSION, /* u16 version */
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32 + 16 * 13, /* Max. number of devices on the bus */
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0x00, /* Interrupt router bus */
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(0x11 << 3) | 0x0, /* Interrupt router dev */
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0, /* IRQs devoted exclusively for PCI */
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PCI_VENDOR_ID_VIA, /* Vendor */
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PCI_DEVICE_ID_VIA_VX900_LPC, /* Device */
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0, /* Miniport */
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
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0x19, /* Checksum (has to be set to some value that
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* would give 0 after the sum of all bytes
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* for this structure (including checksum). */
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{
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/* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
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{0x00, (0x01 << 3) | 0x0, {{LNKH, BITMAP}, {LNKH, BITMAP}, {_OFF, ___OFF}, {_OFF, ___OFF}}, 0x0, 0x0},
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{0x00, (0x03 << 3) | 0x0, {{LNKH, BITMAP}, {LNKH, BITMAP}, {LNKH, BITMAP}, {LNKH, BITMAP}}, 0x0, 0x0},
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{0x00, (0x0a << 3) | 0x0, {{LNKA, BITMAP}, {LNKB, B_SATA}, {LNKC, BITMAP}, {LNKD, BITMAP}}, 0x0, 0x0},
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{0x00, (0x0b << 3) | 0x0, {{LNKA, BITMAP}, {_OFF, ___OFF}, {_OFF, ___OFF}, {_OFF, ___OFF}}, 0x0, 0x0},
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{0x00, (0x0c << 3) | 0x0, {{LNKA, BITMAP}, {_OFF, ___OFF}, {_OFF, ___OFF}, {_OFF, ___OFF}}, 0x0, 0x0},
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{0x00, (0x0d << 3) | 0x0, {{LNKA, BITMAP}, {_OFF, ___OFF}, {_OFF, ___OFF}, {_OFF, ___OFF}}, 0x0, 0x0},
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{0x00, (0x0f << 3) | 0x0, {{LNKB, B_SATA}, {_OFF, ___OFF}, {_OFF, ___OFF}, {_OFF, ___OFF}}, 0x0, 0x0},
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{0x00, (0x10 << 3) | 0x0, {{LNKA, BITMAP}, {LNKB, B_SATA}, {LNKC, BITMAP}, {LNKD, BITMAP}}, 0x0, 0x0},
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{0x00, (0x14 << 3) | 0x0, {{LNKB, B_SATA}, {_OFF, ___OFF}, {_OFF, ___OFF}, {_OFF, ___OFF}}, 0x0, 0x0},
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{0x01, (0x00 << 3) | 0x0, {{LNKH, BITMAP}, {LNKH, BITMAP}, {LNKH, BITMAP}, {LNKH, BITMAP}}, 0x1, 0x0},
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{0x02, (0x00 << 3) | 0x0, {{LNKH, BITMAP}, {LNKH, BITMAP}, {LNKH, BITMAP}, {LNKH, BITMAP}}, 0x2, 0x0},
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{0x03, (0x00 << 3) | 0x0, {{LNKH, BITMAP}, {LNKH, BITMAP}, {LNKH, BITMAP}, {LNKH, BITMAP}}, 0x0, 0x0},
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{0x04, (0x00 << 3) | 0x0, {{LNKH, BITMAP}, {LNKH, BITMAP}, {LNKH, BITMAP}, {LNKH, BITMAP}}, 0x0, 0x0},
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}
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};
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unsigned long write_pirq_routing_table(unsigned long addr)
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{
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return copy_pirq_routing_table(addr, &intel_irq_routing_table);
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}
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@ -1,107 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me@gmail.com>
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*
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* This program is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
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|
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#include <device/device.h>
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#include <device/pci_def.h>
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#include <console/console.h>
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#if CONFIG(VGA_ROM_RUN)
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#include <arch/interrupt.h>
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#include <x86emu/x86emu.h>
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#include <northbridge/via/vx900/vx900.h>
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static int vx900_int15_handler(void)
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{
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int res;
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printk(BIOS_DEBUG, "%s %0x\n", __func__, X86_AX & 0xffff);
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/* Set AX return value here so we don't set it every time. Just set it
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* to something else if the callback is unsupported */
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res = -1;
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switch (X86_AX & 0xffff) {
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#if 0
|
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case 0x5f01:
|
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/* VGA POST - panel type */
|
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/* FIXME: Don't hardcode panel type */
|
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/* Panel Type Number */
|
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X86_CX = 0;
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res = 0;
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break;
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case 0x5f02:
|
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{
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/* Boot device selection */
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X86_BL = INT15_5F02_BL_HWOPT_CRTCONN;
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/* FIXME: or 0 ? */
|
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X86_BH = 0; // INT15_5F02_BH_TV_CONN_DEFAULT;
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X86_EBX = 0; // INT15_5F02_EBX_HDTV_RGB;
|
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X86_ECX = INT15_5F02_ECX_DISPLAY_CRT;
|
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//X86_ECX |= INT15_5F02_ECX_TV_MODE_RGB;
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//X86_ECX |= INT15_5F02_ECX_HDTV_1080P;
|
||||
X86_DL = INT15_5F02_DL_TV_LAYOUT_DEFAULT;
|
||||
res = 0;
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
case 0x5f18:
|
||||
X86_BL = vx900_int15_get_5f18_bl();
|
||||
res = 0;
|
||||
break;
|
||||
#if 0
|
||||
case 0x5f2a:
|
||||
/* Get SSC Control Settings */
|
||||
/* FIXME: No idea what this does. Just disable this feature
|
||||
* for now */
|
||||
X86_CX = INT15_5F2A_CX_SSC_ENABLE;
|
||||
res = 0;
|
||||
break;
|
||||
case 0x5f2b:
|
||||
/* Engine clock setting */
|
||||
/* FIXME: ECLK fixed 250MHz ? */
|
||||
X86_EBX = INT15_5F2B_EBX_ECLK_250MHZ;
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
printk(BIOS_DEBUG, "Unsupported INT15 call %04x!\n",
|
||||
X86_AX & 0xffff);
|
||||
X86_AX = 0;
|
||||
res = -1;
|
||||
break;
|
||||
}
|
||||
|
||||
if (res == 0)
|
||||
X86_AX = 0x5f;
|
||||
else
|
||||
X86_AX = 0;
|
||||
return X86_AX;
|
||||
}
|
||||
#endif
|
||||
|
||||
static void mainboard_enable(struct device *dev)
|
||||
{
|
||||
(void)dev;
|
||||
|
||||
#if CONFIG(VGA_ROM_RUN)
|
||||
printk(BIOS_DEBUG, "Installing INT15 handler...\n");
|
||||
mainboard_interrupt_handlers(0x15, &vx900_int15_handler);
|
||||
#endif
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
CHIP_NAME("VIA EPIA-M850 Mainboard")
|
||||
.enable_dev = mainboard_enable,
|
||||
};
|
||||
|
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@ -1,98 +0,0 @@
|
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/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011-2012 Alexandru Gagniuc <mr.nuke.me@gmail.com>
|
||||
*
|
||||
* This program is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Inspired from the EPIA-M700
|
||||
*/
|
||||
#include <stdint.h>
|
||||
#include <console/console.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <lib.h>
|
||||
#include <cpu/x86/bist.h>
|
||||
#include <timestamp.h>
|
||||
#include <cbmem.h>
|
||||
|
||||
#include <northbridge/via/vx900/early_vx900.h>
|
||||
#include <northbridge/via/vx900/raminit.h>
|
||||
#include <superio/fintek/common/fintek.h>
|
||||
#include <superio/fintek/f81865f/f81865f.h>
|
||||
|
||||
#define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1)
|
||||
|
||||
/* cache_as_ram.inc jumps to here. */
|
||||
void main(unsigned long bist)
|
||||
{
|
||||
u32 tolm;
|
||||
|
||||
timestamp_init(timestamp_get());
|
||||
timestamp_add_now(TS_START_ROMSTAGE);
|
||||
|
||||
/* First thing we need to do on the VX900, before anything else */
|
||||
vx900_enable_pci_config_space();
|
||||
|
||||
/* Serial console is easy to take care of */
|
||||
fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
console_init();
|
||||
printk(BIOS_DEBUG, "Console initialized.\n");
|
||||
|
||||
vx900_cpu_bus_interface_setup();
|
||||
|
||||
/* Be smart. Get this info */
|
||||
vx900_print_strapping_info();
|
||||
/* DEVEL helper */
|
||||
vx900_disable_auto_reboot();
|
||||
/* Halt if there was a built-in self test failure. */
|
||||
report_bist_failure(bist);
|
||||
|
||||
/* Oh, almighty, give us the SMBUS */
|
||||
enable_smbus();
|
||||
|
||||
timestamp_add_now(TS_BEFORE_INITRAM);
|
||||
/* Now we can worry about raminit.
|
||||
* This board only has DDR3, so no need to worry about which DRAM type
|
||||
* to use */
|
||||
dimm_layout dimms = { {0x50, 0x51, SPD_END_LIST} };
|
||||
vx900_init_dram_ddr3(&dimms);
|
||||
timestamp_add_now(TS_AFTER_INITRAM);
|
||||
|
||||
/* TODO: All these ram_checks are here to ensure we test most of the RAM
|
||||
* below 4G. They should not be needed once VX900 raminit is stable */
|
||||
ram_check(0, 0x80);
|
||||
ram_check(512 << 10, 0x80);
|
||||
ram_check((1 << 20) - (1 << 10), 0x80);
|
||||
ram_check((1 << 24), 0x80);
|
||||
ram_check((512 + 256 - 1) << 20, 0x80);
|
||||
ram_check(0x80c0000, 0x80);
|
||||
tolm = vx900_get_tolm () << 20;
|
||||
if (tolm > (1 * (u32) GiB))
|
||||
ram_check(1024 << 10, 0x80);
|
||||
if (tolm > (2 * (u32) GiB))
|
||||
ram_check(2048 << 20, 0x80);
|
||||
|
||||
printk(BIOS_DEBUG, "We passed RAM verify\n");
|
||||
|
||||
/* FIXME: read fb_size from CMOS, but until that is implemented, start
|
||||
* from 512MB */
|
||||
vx900_set_chrome9hd_fb_size (512);
|
||||
|
||||
/* We got RAM working, now we can write the timestamps to RAM */
|
||||
cbmem_recovery(0);
|
||||
|
||||
/* FIXME: See if this is needed or take this out please */
|
||||
/* Disable Memcard and SDIO */
|
||||
pci_or_config8(LPC, 0x51, (1 << 7) | (1 << 4));
|
||||
}
|
||||
Loading…
Reference in New Issue