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small fixes to get Ward Vandewege's Tyan board booting. 

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2251 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer 2006-04-11 18:36:42 +00:00
parent 4b8cf1d30a
commit fbce0ffb92
2 changed files with 5 additions and 4 deletions
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6
src/northbridge/amd/amdk8/incoherent_ht.c
View File

@ -275,12 +275,12 @@ static int ht_optimize_link(
static void ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, static void ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus,
unsigned offset_unitid, struct sys_info *sysinfo); unsigned offset_unitid, struct sys_info *sysinfo);
static int scan_pci_bus( unsigned bus , struct sys_info *sysinfo) static int scan_pci_bus(unsigned bus, struct sys_info *sysinfo)
#else #else
static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus,
unsigned offset_unitid); unsigned offset_unitid);
static int scan_pci_bus( unsigned bus) static int scan_pci_bus(unsigned bus)
#endif #endif
{ {
/* Here we already can access PCI_DEV(bus, 0, 0) to /* Here we already can access PCI_DEV(bus, 0, 0) to
@ -467,7 +467,7 @@ static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned of
* retrain, so lets knock it down and see * retrain, so lets knock it down and see
* if its transient * if its transient
*/ */
ctrl |= ((1 << 6) | (1 <<8)); // Link fail + Crc ctrl |= ((1 << 4) | (1 <<8)); // Link fail + Crc
pci_write_config16(udev, upos + LINK_CTRL(uoffs), ctrl); pci_write_config16(udev, upos + LINK_CTRL(uoffs), ctrl);
ctrl = pci_read_config16(udev, upos + LINK_CTRL(uoffs)); ctrl = pci_read_config16(udev, upos + LINK_CTRL(uoffs));
if (ctrl & ((1 << 4) | (1 << 8))) { if (ctrl & ((1 << 4) | (1 << 8))) {

3
src/southbridge/amd/amd8111/amd8111_pci.c
View File

@ -23,7 +23,8 @@ static void pci_init(struct device *dev)
dword |= (1<<17); /* System */ dword |= (1<<17); /* System */
dword |= (1<<21); /* Master abort */ dword |= (1<<21); /* Master abort */
// dword &= ~(1<<21); /* Master abort */ // dword &= ~(1<<21); /* Master abort */
dword |= (1<<27); /* Discard timer */ // dword |= (1<<27); /* Discard timer */
dword &= ~(1<<27); /* Discard timer */
dword |= (1<<26); /* DTSTAT error clear */ dword |= (1<<26); /* DTSTAT error clear */
pci_write_config32(dev, 0x3c, dword); pci_write_config32(dev, 0x3c, dword);