intel/sandybridge intel/ivybridge: Use MMCONF_SUPPORT_DEFAULT
Change all PCI configuration accesses to MMIO on all boards with SandyBridge and IvyBridge. To enable MMIO style access, add explicit PCI IO config write in the bootblock. Change-Id: I8f957a80bf57df000897c5a080dd5ff131b1ec0d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3576 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.huber@secunet.com>
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@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select HAVE_ACPI_TABLES
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select HAVE_OPTION_TABLE
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select HAVE_ACPI_RESUME
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select MMCONF_SUPPORT
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select HAVE_SMI_HANDLER
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select GFXUMA
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select CHROMEOS
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@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select HAVE_ACPI_TABLES
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select HAVE_OPTION_TABLE
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select HAVE_ACPI_RESUME
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select MMCONF_SUPPORT
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select HAVE_SMI_HANDLER
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select GFXUMA
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select CHROMEOS
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@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select HAVE_ACPI_TABLES
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select HAVE_OPTION_TABLE
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select HAVE_ACPI_RESUME
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select MMCONF_SUPPORT
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select HAVE_SMI_HANDLER
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select GFXUMA
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select CHROMEOS
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@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select HAVE_ACPI_TABLES
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select HAVE_OPTION_TABLE
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select HAVE_ACPI_RESUME
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select MMCONF_SUPPORT
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select HAVE_SMI_HANDLER
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select GFXUMA
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select CHROMEOS
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@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select HAVE_ACPI_TABLES
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select HAVE_OPTION_TABLE
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select HAVE_ACPI_RESUME
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select MMCONF_SUPPORT
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select GFXUMA
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#select CHROMEOS
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select EXTERNAL_MRC_BLOB
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@ -12,7 +12,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select HAVE_ACPI_TABLES
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select HAVE_OPTION_TABLE
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select HAVE_ACPI_RESUME
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select MMCONF_SUPPORT
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select HAVE_SMI_HANDLER
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select GFXUMA
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select EXTERNAL_MRC_BLOB
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@ -12,7 +12,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select HAVE_OPTION_TABLE
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select MMCONF_SUPPORT
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select NORTHBRIDGE_INTEL_SANDYBRIDGE
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select SOUTHBRIDGE_INTEL_BD82X6X
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select SUPERIO_SMSC_MEC1308
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@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select HAVE_OPTION_TABLE
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select MMCONF_SUPPORT
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select NORTHBRIDGE_INTEL_SANDYBRIDGE
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select SOUTHBRIDGE_INTEL_BD82X6X
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select SUPERIO_ITE_IT8772F
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@ -20,11 +20,15 @@
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config NORTHBRIDGE_INTEL_SANDYBRIDGE
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bool
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select CACHE_MRC_BIN
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select MMCONF_SUPPORT
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select MMCONF_SUPPORT_DEFAULT
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select CPU_INTEL_MODEL_206AX
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config NORTHBRIDGE_INTEL_IVYBRIDGE
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bool
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select CACHE_MRC_BIN
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select MMCONF_SUPPORT
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select MMCONF_SUPPORT_DEFAULT
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select CPU_INTEL_MODEL_306AX
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if NORTHBRIDGE_INTEL_SANDYBRIDGE
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@ -103,6 +107,10 @@ endif
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if NORTHBRIDGE_INTEL_SANDYBRIDGE || NORTHBRIDGE_INTEL_IVYBRIDGE
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config BOOTBLOCK_NORTHBRIDGE_INIT
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string
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default "northbridge/intel/sandybridge/bootblock.c"
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config DCACHE_RAM_MRC_VAR_SIZE
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hex
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default 0x4000
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@ -0,0 +1,26 @@
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#include <arch/io.h>
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/* Just re-define this instead of including sandybridge.h. It blows up romcc. */
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#define PCIEXBAR 0x60
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static void bootblock_northbridge_init(void)
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{
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uint32_t reg;
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/*
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* The "io" variant of the config access is explicitly used to
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* setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT_DEFAULT is set to
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* to true. That way all subsequent non-explicit config accesses use
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* MCFG. This code also assumes that bootblock_northbridge_init() is
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* the first thing called in the non-asm boot block code. The final
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* assumption is that no assembly code is using the
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* CONFIG_MMCONF_SUPPORT_DEFAULT option to do PCI config acceses.
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*
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* The PCIEXBAR is assumed to live in the memory mapped IO space under
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* 4GiB.
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*/
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reg = 0;
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pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR + 4, reg);
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reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */
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pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR, reg);
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}
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@ -49,8 +49,6 @@ static void sandybridge_setup_bars(void)
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pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4, (0LL+DEFAULT_EPBAR) >> 32);
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pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, DEFAULT_MCHBAR | 1);
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pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4, (0LL+DEFAULT_MCHBAR) >> 32);
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pci_write_config32(PCI_DEV(0, 0x00, 0), PCIEXBAR, DEFAULT_PCIEXBAR | 5); /* 64MB - busses 0-63 */
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pci_write_config32(PCI_DEV(0, 0x00, 0), PCIEXBAR + 4, (0LL+DEFAULT_PCIEXBAR) >> 32);
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pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, DEFAULT_DMIBAR | 1);
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pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, (0LL+DEFAULT_DMIBAR) >> 32);
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