mb/google/skyrim/var/winterhold: Update DPTC settings for final version
Follow thermal team's request on b/248086651 comment#32. Update the thermal table setting for each mode and the conditions of temperature switching. BUG=b:248086651,b:241180483 TEST=emerge-skyrim coreboot Change-Id: Ibcf6c110029d39bdc6bfaf46c234a4073ee69f30 Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73732 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com>
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@ -30,15 +30,15 @@ Scope (\_SB)
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// Table A/B
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If ((\_SB.PRTN == 0) || (\_SB.PRTN == 1)) {
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// AMB sensor trigger point
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// 44C will store 117(0x75) in mapped memory
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// 44C=317K, 317-200(offset)=117(0x75)
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If (\_SB.PCI0.LPCB.EC0.TIN4 >= 117) {
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// 43C will store 116(0x74) in mapped memory
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// 43C=316K, 316-200(offset)=116(0x74)
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If (\_SB.PCI0.LPCB.EC0.TIN4 >= 116) {
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\_SB.DTTB()
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\_SB.PRTN = 1
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Return (0)
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}
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// AMB sensor release point
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If ((\_SB.PCI0.LPCB.EC0.TIN4 <= 113)) {
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If ((\_SB.PCI0.LPCB.EC0.TIN4 <= 112)) {
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\_SB.DDEF()
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\_SB.PRTN = 0
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Return (0)
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@ -37,10 +37,10 @@ chip soc/amd/mendocino
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register "slow_ppt_time_constant_s" = "5"
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register "stt_min_limit" = "15000"
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register "stt_m1" = "0x18F"
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register "stt_m2" = "0x48F"
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register "stt_c_apu" = "0xECC5"
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register "stt_skin_temp_apu" = "0x3200"
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register "stt_m1" = "0xAE"
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register "stt_m2" = "0xB8F"
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register "stt_c_apu" = "0xC13B"
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register "stt_skin_temp_apu" = "0x3000"
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# Set Dynamic DPTC thermal profile confiuration. Table B
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register "fast_ppt_limit_mW_B" = "15000"
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@ -48,10 +48,10 @@ chip soc/amd/mendocino
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register "slow_ppt_time_constant_s_B" = "5"
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register "stt_min_limit_B" = "10500"
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register "stt_m1_B" = "0x18F"
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register "stt_m2_B" = "0x48F"
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register "stt_c_apu_B" = "0xECC5"
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register "stt_skin_temp_apu_B" = "0x3300"
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register "stt_m1_B" = "0xAE"
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register "stt_m2_B" = "0xB8F"
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register "stt_c_apu_B" = "0xC13B"
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register "stt_skin_temp_apu_B" = "0x3000"
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# Set Dynamic DPTC thermal profile confiuration. Table C
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register "fast_ppt_limit_mW_C" = "30000"
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@ -59,10 +59,10 @@ chip soc/amd/mendocino
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register "slow_ppt_time_constant_s_C" = "5"
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register "stt_min_limit_C" = "15000"
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register "stt_m1_C" = "0x152"
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register "stt_m2_C" = "0x4AE"
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register "stt_c_apu_C" = "0xEE94"
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register "stt_skin_temp_apu_C" = "0x3200"
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register "stt_m1_C" = "0x129"
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register "stt_m2_C" = "0xAF6"
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register "stt_c_apu_C" = "0xC3D2"
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register "stt_skin_temp_apu_C" = "0x3000"
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# Set Dynamic DPTC thermal profile confiuration. Table D
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register "fast_ppt_limit_mW_D" = "15000"
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@ -70,10 +70,10 @@ chip soc/amd/mendocino
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register "slow_ppt_time_constant_s_D" = "5"
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register "stt_min_limit_D" = "10500"
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register "stt_m1_D" = "0x152"
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register "stt_m2_D" = "0x4AE"
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register "stt_c_apu_D" = "0xEE94"
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register "stt_skin_temp_apu_D" = "0x3300"
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register "stt_m1_D" = "0x129"
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register "stt_m2_D" = "0xAF6"
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register "stt_c_apu_D" = "0xC3D2"
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register "stt_skin_temp_apu_D" = "0x3000"
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# Set Dynamic DPTC thermal profile confiuration. Table E
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register "fast_ppt_limit_mW_E" = "24000"
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@ -81,9 +81,9 @@ chip soc/amd/mendocino
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register "slow_ppt_time_constant_s_E" = "5"
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register "stt_min_limit_E" = "12000"
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register "stt_m1_E" = "0x18F"
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register "stt_m2_E" = "0x48F"
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register "stt_c_apu_E" = "0xECC5"
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register "stt_m1_E" = "0xAE"
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register "stt_m2_E" = "0xB8F"
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register "stt_c_apu_E" = "0xC13B"
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register "stt_skin_temp_apu_E" = "0x2F00"
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@ -93,10 +93,10 @@ chip soc/amd/mendocino
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register "slow_ppt_time_constant_s_F" = "5"
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register "stt_min_limit_F" = "8000"
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register "stt_m1_F" = "0x18F"
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register "stt_m2_F" = "0x48F"
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register "stt_c_apu_F" = "0xECC5"
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register "stt_skin_temp_apu_F" = "0x3000"
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register "stt_m1_F" = "0xAE"
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register "stt_m2_F" = "0xB8F"
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register "stt_c_apu_F" = "0xC13B"
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register "stt_skin_temp_apu_F" = "0x2F00"
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register "i2c[0]" = "{
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.speed = I2C_SPEED_FAST,
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