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mb/google/slippy: Fix overridden southbridge settings 

To take any effect, a `chip` entry in a devicetree or overridetree
always needs a `device` node.

Change-Id: I158459e28dc8c63df4f1d58b30017868a57e5602
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57466
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Nico Huber 2021-09-07 16:03:44 +02:00 committed by Felix Held
parent da3ef13d27
commit fc726b9ea0
3 changed files with 23 additions and 13 deletions
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6
src/mainboard/google/slippy/variants/falco/overridetree.cb
View File

@ -13,8 +13,10 @@ chip northbridge/intel/haswell
chip southbridge/intel/lynxpoint
# Disable PCIe CLKOUT 1-5 and CLKOUT_XDP
register "icc_clock_disable" = "0x013e0000"
device pci 16.0 on # Management Engine Interface 1
# Disable PCIe CLKOUT 1-5 and CLKOUT_XDP
register "icc_clock_disable" = "0x013e0000"
end
end
end
end

14
src/mainboard/google/slippy/variants/peppy/overridetree.cb
View File

@ -13,12 +13,16 @@ chip northbridge/intel/haswell
chip southbridge/intel/lynxpoint
# DTLE DATA / EDGE values
register "sata_port0_gen3_dtle" = "0x5"
register "sata_port1_gen3_dtle" = "0x5"
device pci 1f.2 on # SATA Controller
# DTLE DATA / EDGE values
register "sata_port0_gen3_dtle" = "0x5"
register "sata_port1_gen3_dtle" = "0x5"
end
# Disable PCIe CLKOUT 2-5 and CLKOUT_XDP
register "icc_clock_disable" = "0x013c0000"
device pci 16.0 on # Management Engine Interface 1
# Disable PCIe CLKOUT 2-5 and CLKOUT_XDP
register "icc_clock_disable" = "0x013c0000"
end
end
end
end

16
src/mainboard/google/slippy/variants/wolf/overridetree.cb
View File

@ -13,14 +13,18 @@ chip northbridge/intel/haswell
chip southbridge/intel/lynxpoint
register "sata_devslp_disable" = "0x1"
device pci 1f.2 on # SATA Controller
register "sata_devslp_disable" = "0x1"
# DTLE DATA / EDGE values
register "sata_port0_gen3_dtle" = "0x5"
register "sata_port1_gen3_dtle" = "0x5"
# DTLE DATA / EDGE values
register "sata_port0_gen3_dtle" = "0x5"
register "sata_port1_gen3_dtle" = "0x5"
end
# Disable PCIe CLKOUT 2-5 and CLKOUT_XDP
register "icc_clock_disable" = "0x013c0000"
device pci 16.0 on # Management Engine Interface 1
# Disable PCIe CLKOUT 2-5 and CLKOUT_XDP
register "icc_clock_disable" = "0x013c0000"
end
end
end
end