mb/google/slippy: Fix overridden southbridge settings

To take any effect, a `chip` entry in a devicetree or overridetree
always needs a `device` node.

Change-Id: I158459e28dc8c63df4f1d58b30017868a57e5602
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57466
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/google/slippy/variants/falco/overridetree.cb

@@ -13,8 +13,10 @@ chip northbridge/intel/haswell
 
 		chip southbridge/intel/lynxpoint
 
+			device pci 16.0 on # Management Engine Interface 1
 				# Disable PCIe CLKOUT 1-5 and CLKOUT_XDP
 				register "icc_clock_disable" = "0x013e0000"
 			end
 		end
+	end
 end

src/mainboard/google/slippy/variants/peppy/overridetree.cb

@@ -13,12 +13,16 @@ chip northbridge/intel/haswell
 
 		chip southbridge/intel/lynxpoint
 
+			device pci 1f.2 on # SATA Controller
 				# DTLE DATA / EDGE values
 				register "sata_port0_gen3_dtle" = "0x5"
 				register "sata_port1_gen3_dtle" = "0x5"
+			end
 
+			device pci 16.0 on # Management Engine Interface 1
 				# Disable PCIe CLKOUT 2-5 and CLKOUT_XDP
 				register "icc_clock_disable" = "0x013c0000"
 			end
 		end
+	end
 end

src/mainboard/google/slippy/variants/wolf/overridetree.cb

@@ -13,14 +13,18 @@ chip northbridge/intel/haswell
 
 		chip southbridge/intel/lynxpoint
 
+			device pci 1f.2 on # SATA Controller
 				register "sata_devslp_disable" = "0x1"
 
 				# DTLE DATA / EDGE values
 				register "sata_port0_gen3_dtle" = "0x5"
 				register "sata_port1_gen3_dtle" = "0x5"
+			end
 
+			device pci 16.0 on # Management Engine Interface 1
 				# Disable PCIe CLKOUT 2-5 and CLKOUT_XDP
 				register "icc_clock_disable" = "0x013c0000"
 			end
 		end
+	end
 end