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soc/amd/stoneyridge: add resources during read_resources() 

The chipset code was incorrectly adding memory resources
to the domain device after resource allocation occurred.
It's not possible to get the correct view of the address space,
and it's generally incorrect to not add resources during
read_resources(). This change fixes the order by adding resources
during read_resources().

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I532f508936d5ec154cbcb3538949316ae4851105
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41369
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Furquan Shaikh 2020-05-13 12:14:11 -07:00 committed by Aaron Durbin
parent ffa5e8ddcf
commit fc752b6918
3 changed files with 6 additions and 6 deletions
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4
src/soc/amd/stoneyridge/chip.c
View File

@ -96,8 +96,8 @@ const char *soc_acpi_name(const struct device *dev)
}; };
struct device_operations pci_domain_ops = { struct device_operations pci_domain_ops = {
.read_resources = pci_domain_read_resources, .read_resources = domain_read_resources,
.set_resources = domain_set_resources, .set_resources = pci_domain_set_resources,
.enable_resources = domain_enable_resources, .enable_resources = domain_enable_resources,
.scan_bus = pci_domain_scan_bus, .scan_bus = pci_domain_scan_bus,
.acpi_name = soc_acpi_name, .acpi_name = soc_acpi_name,

2
src/soc/amd/stoneyridge/include/soc/northbridge.h
View File

@ -84,7 +84,7 @@
#define CMP_CAP_MASK 0xff #define CMP_CAP_MASK 0xff
void domain_enable_resources(struct device *dev); void domain_enable_resources(struct device *dev);
void domain_set_resources(struct device *dev); void domain_read_resources(struct device *dev);
void fam15_finalize(void *chip_info); void fam15_finalize(void *chip_info);
void set_warm_reset_flag(void); void set_warm_reset_flag(void);
int is_warm_reset(void); int is_warm_reset(void);

6
src/soc/amd/stoneyridge/northbridge.c
View File

@ -414,7 +414,7 @@ void domain_enable_resources(struct device *dev)
do_agesawrapper(AMD_INIT_MID, "amdinitmid"); do_agesawrapper(AMD_INIT_MID, "amdinitmid");
} }
void domain_set_resources(struct device *dev) void domain_read_resources(struct device *dev)
{ {
uint64_t uma_base = get_uma_base(); uint64_t uma_base = get_uma_base();
uint32_t uma_size = get_uma_size(); uint32_t uma_size = get_uma_size();
@ -424,6 +424,8 @@ void domain_set_resources(struct device *dev)
uint64_t high_mem_useable; uint64_t high_mem_useable;
int idx = 0x10; int idx = 0x10;
pci_domain_read_resources(dev);
/* 0x0 -> 0x9ffff */ /* 0x0 -> 0x9ffff */
ram_resource(dev, idx++, 0, 0xa0000 / KiB); ram_resource(dev, idx++, 0, 0xa0000 / KiB);
@ -462,8 +464,6 @@ void domain_set_resources(struct device *dev)
uma_size / KiB); uma_size / KiB);
} }
} }
assign_resources(dev->link_list);
} }
/********************************************************************* /*********************************************************************