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mb/google/guybrush/var/dewatt: update USB3 settings for passing SI 

Update tx/rx term control to 3 for passing USB3 port 0/1 SI.

b:199468920
TEST= emerge-guybrush coreboot; build and pass USB3 SI.

Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Change-Id: I637207d7c657f6dd71d70694f9a5fb35f8294b64
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60809
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
This commit is contained in:
Kenneth Chan 2022-01-06 10:22:34 +08:00 committed by Raul Rangel
parent e3411cda2e
commit fc7a40fad9
1 changed files with 15 additions and 1 deletions
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16
src/mainboard/google/guybrush/variants/dewatt/overridetree.cb
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@ -18,7 +18,7 @@ chip soc/amd/cezanne
register "telemetry_vddcrsocfull_scale_current_mA" = "31481" #mA register "telemetry_vddcrsocfull_scale_current_mA" = "31481" #mA
register "telemetry_vddcrsocoffset" = "193" register "telemetry_vddcrsocoffset" = "193"
#USB 2.0 phy config #USB 2/3 phy config
register "usb_phy" = "{ register "usb_phy" = "{
/* Left USB C0 Port */ /* Left USB C0 Port */
.Usb2PhyPort[0] = { .Usb2PhyPort[0] = {
@ -56,6 +56,20 @@ chip soc/amd/cezanne
.txhsxvtune = 3, .txhsxvtune = 3,
.txrestune = 1, .txrestune = 1,
}, },
/* Left USB C0 Port */
.Usb3PhyPort[0] = {
.tx_term_ctrl=3,
.rx_term_ctrl=3,
.tx_vboost_lvl_en=1,
.tx_vboost_lvl=5,
},
/* Left USB A0 Port */
.Usb3PhyPort[1] = {
.tx_term_ctrl=3,
.rx_term_ctrl=3,
.tx_vboost_lvl_en=1,
.tx_vboost_lvl=5,
},
}" }"
# general purpose PCIe clock output configuration # general purpose PCIe clock output configuration