mb/lenovo: Add additional FMAPs for stripped ME

Make it easier to use measured boot with stripped ME by
providing the corresponding FMAPs.

Change-Id: I1763583a42bbc91e6acc06b262deab10d34447a3
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39798
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Marcello Sylvester Bauer <sylv@sylv.io>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
This commit is contained in:
Patrick Rudolph 2020-03-24 08:29:08 +01:00 committed by Patrick Georgi
parent 45a354fe78
commit fc8867c3d8
7 changed files with 147 additions and 0 deletions

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@ -0,0 +1,21 @@
FLASH@0xff400000 0xc00000 {
SI_ALL 0x20000 {
SI_DESC 0x1000
SI_GBE 0x2000
SI_ME
}
SI_BIOS 0xbe0000 {
UNIFIED_MRC_CACHE 0x20000 {
RECOVERY_MRC_CACHE 0x10000
RW_MRC_CACHE 0x10000
}
WP_RO {
FMAP 0x800
RO_FRID 0x40
RO_PADDING 0x7c0
GBB 0x1e000
COREBOOT(CBFS)
}
}
}

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@ -0,0 +1,21 @@
FLASH@0xff400000 0xc00000 {
SI_ALL 0x20000 {
SI_DESC 0x1000
SI_GBE 0x2000
SI_ME
}
SI_BIOS 0xbe0000 {
UNIFIED_MRC_CACHE 0x20000 {
RECOVERY_MRC_CACHE 0x10000
RW_MRC_CACHE 0x10000
}
WP_RO {
FMAP 0x800
RO_FRID 0x40
RO_PADDING 0x7c0
GBB 0x1e000
COREBOOT(CBFS)
}
}
}

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@ -0,0 +1,21 @@
FLASH@0xff400000 0xc00000 {
SI_ALL 0x20000 {
SI_DESC 0x1000
SI_GBE 0x2000
SI_ME
}
SI_BIOS 0xbe0000 {
UNIFIED_MRC_CACHE 0x20000 {
RECOVERY_MRC_CACHE 0x10000
RW_MRC_CACHE 0x10000
}
WP_RO {
FMAP 0x800
RO_FRID 0x40
RO_PADDING 0x7c0
GBB 0x1e000
COREBOOT(CBFS)
}
}
}

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@ -0,0 +1,21 @@
FLASH@0xff400000 0xc00000 {
SI_ALL 0x20000 {
SI_DESC 0x1000
SI_GBE 0x2000
SI_ME
}
SI_BIOS 0xbe0000 {
UNIFIED_MRC_CACHE 0x20000 {
RECOVERY_MRC_CACHE 0x10000
RW_MRC_CACHE 0x10000
}
WP_RO {
FMAP 0x800
RO_FRID 0x40
RO_PADDING 0x7c0
GBB 0x1e000
COREBOOT(CBFS)
}
}
}

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@ -0,0 +1,21 @@
FLASH@0xff400000 0xc00000 {
SI_ALL 0x20000 {
SI_DESC 0x1000
SI_GBE 0x2000
SI_ME
}
SI_BIOS 0xbe0000 {
UNIFIED_MRC_CACHE 0x20000 {
RECOVERY_MRC_CACHE 0x10000
RW_MRC_CACHE 0x10000
}
WP_RO {
FMAP 0x800
RO_FRID 0x40
RO_PADDING 0x7c0
GBB 0x1e000
COREBOOT(CBFS)
}
}
}

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@ -0,0 +1,21 @@
FLASH@0xff400000 0xc00000 {
SI_ALL 0x20000 {
SI_DESC 0x1000
SI_GBE 0x2000
SI_ME
}
SI_BIOS 0xbe0000 {
UNIFIED_MRC_CACHE 0x20000 {
RECOVERY_MRC_CACHE 0x10000
RW_MRC_CACHE 0x10000
}
WP_RO {
FMAP 0x800
RO_FRID 0x40
RO_PADDING 0x7c0
GBB 0x1e000
COREBOOT(CBFS)
}
}
}

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@ -0,0 +1,21 @@
FLASH@0xff400000 0xc00000 {
SI_ALL 0x20000 {
SI_DESC 0x1000
SI_GBE 0x2000
SI_ME
}
SI_BIOS 0xbe0000 {
UNIFIED_MRC_CACHE 0x20000 {
RECOVERY_MRC_CACHE 0x10000
RW_MRC_CACHE 0x10000
}
WP_RO {
FMAP 0x800
RO_FRID 0x40
RO_PADDING 0x7c0
GBB 0x1e000
COREBOOT(CBFS)
}
}
}