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corrected irq and mp table according to new bus enumeration 

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1542 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Li-Ta Lo 2004-04-28 18:49:24 +00:00
parent 500497fc34
commit fcdd571aee
3 changed files with 28 additions and 21 deletions
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25
src/mainboard/ibm/e325/irq_tables.c
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@ -1,6 +1,7 @@
#include <arch/pirq_routing.h> #include <arch/pirq_routing.h>
#include <device/pci.h> #include <device/pci.h>
#define IRQ_SLOT_COUNT 12
#define IRQ_ROUTER_BUS 0 #define IRQ_ROUTER_BUS 0
#define IRQ_ROUTER_DEVFN PCI_DEVFN(4,3) #define IRQ_ROUTER_DEVFN PCI_DEVFN(4,3)
#define IRQ_ROUTER_VENDOR 0x1022 #define IRQ_ROUTER_VENDOR 0x1022
@ -26,31 +27,31 @@ const struct irq_routing_table intel_irq_routing_table = {
IRQ_ROUTER_DEVICE, /* Device */ IRQ_ROUTER_DEVICE, /* Device */
0x00, /* Crap (miniport) */ 0x00, /* Crap (miniport) */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
0x45, /* u8 checksum , mod 256 checksum must give zero */ 0x34, /* u8 checksum , mod 256 checksum must give zero */
{ /* slot(0=onboard), devfn, irqlinks (line id, 0=not routed) */ { /* slot(0=onboard), devfn, irqlinks (line id, 0=not routed) */
/* Northbridge, Node 0 */ /* Northbridge, Node 0 */
IRQ_SLOT(0x0, 0x00,0x18,0x0, 0,0,0,0), IRQ_SLOT(0x0, 0x00,0x18,0x0, 0,0,0,0),
/* AMD-8131 PCI-X Bridge */ /* AMD-8131 PCI-X Bridge */
IRQ_SLOT(0x0, 0x00,0x01,0x0, 0,0,0,0), IRQ_SLOT(0x0, 0x01,0x01,0x0, 0,0,0,0),
/* Onboard LSI SCSI Controller */ /* Onboard LSI SCSI Controller */
IRQ_SLOT(0x0, 0x01,0x02,0x0, 3,0,0,0), IRQ_SLOT(0x0, 0x02,0x02,0x0, 3,0,0,0),
/* Onboard Broadcom NICs */ /* Onboard Broadcom NICs */
IRQ_SLOT(0x0, 0x01,0x01,0x0, 1,2,0,0), IRQ_SLOT(0x0, 0x02,0x01,0x0, 1,2,0,0),
/* AMD-8131 PCI-X Bridge */ /* AMD-8131 PCI-X Bridge */
IRQ_SLOT(0x0, 0x00,0x02,0x0, 0,0,0,0), IRQ_SLOT(0x0, 0x01,0x02,0x0, 0,0,0,0),
/* PCI Slot 1-2 */ /* PCI Slot 1-2 */
IRQ_SLOT(0x1, 0x02,0x03,0x0, 1,2,3,4), IRQ_SLOT(0x1, 0x03,0x03,0x0, 1,2,3,4),
IRQ_SLOT(0x2, 0x02,0x04,0x0, 2,3,4,1), IRQ_SLOT(0x2, 0x03,0x04,0x0, 2,3,4,1),
/* AMD-8111 PCI Bridge */ /* AMD-8111 PCI Bridge */
IRQ_SLOT(0x0, 0x00,0x03,0x0, 0,0,0,0), IRQ_SLOT(0x0, 0x01,0x03,0x0, 0,0,0,0),
/* USB Controller */ /* USB Controller */
IRQ_SLOT(0x0, 0x03,0x00,0x0, 0,0,0,4), IRQ_SLOT(0x0, 0x04,0x00,0x0, 0,0,0,4),
/* ATI Rage XL VGA */ /* ATI Rage XL VGA */
IRQ_SLOT(0x0, 0x03,0x05,0x0, 1,0,0,0), IRQ_SLOT(0x0, 0x04,0x05,0x0, 1,0,0,0),
/* AMD-8111 LPC Dridge */ /* AMD-8111 LPC Dridge */
IRQ_SLOT(0x0, 0x00,0x04,0x0, 0,0,0,0), IRQ_SLOT(0x0, 0x01,0x04,0x0, 0,0,0,0),
/* Northbridge, Node 1 */ /* Northbridge, Node 1 */
IRQ_SLOT(0x0, 0x00,0x18,0x0, 0,0,0,0), IRQ_SLOT(0x0, 0x00,0x19,0x0, 0,0,0,0),
} }
}; };

8
src/mainboard/ibm/e325/mainboard.c
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@ -272,13 +272,19 @@ static struct device_operations mainboard_operations = {
static void enumerate(struct chip *chip) static void enumerate(struct chip *chip)
{ {
struct chip *child; struct chip *child;
if (chip->control && chip->control->name) {
printk_debug("Enumerating: %s\n", chip->control->name);
}
dev_root.ops = &mainboard_operations; dev_root.ops = &mainboard_operations;
chip->dev = &dev_root; chip->dev = &dev_root;
chip->bus = 0; chip->bus = 0;
for(child = chip->children; child; child = child->next) { for (child = chip->children; child; child = child->next) {
child->bus = &dev_root.link[0]; child->bus = &dev_root.link[0];
} }
} }
struct chip_control mainboard_ibm_e325_control = { struct chip_control mainboard_ibm_e325_control = {
.enumerate = enumerate, .enumerate = enumerate,
.name = "IBM E325 mainboard ", .name = "IBM E325 mainboard ",

16
src/mainboard/ibm/e325/mptable.c
View File

@ -41,34 +41,34 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
device_t dev; device_t dev;
/* 8111 */ /* 8111 */
dev = dev_find_slot(0, PCI_DEVFN(0x03,0)); dev = dev_find_slot(1, PCI_DEVFN(0x03,0));
if (dev) { if (dev) {
bus_8111_0 = pci_read_config8(dev, PCI_PRIMARY_BUS); bus_8111_0 = pci_read_config8(dev, PCI_PRIMARY_BUS);
bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_isa++; bus_isa++;
} else { } else {
printk_debug("ERROR - could not find PCI 0:03.0, using defaults\n"); printk_debug("ERROR - could not find PCI 1:03.0, using defaults\n");
bus_8111_1 = 4; bus_8111_1 = 4;
bus_isa = 5; bus_isa = 5;
} }
/* 8131-1 */ /* 8131-1 */
dev = dev_find_slot(0, PCI_DEVFN(0x01,0)); dev = dev_find_slot(1, PCI_DEVFN(0x01,0));
if (dev) { if (dev) {
bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
} else { } else {
printk_debug("ERROR - could not find PCI 0:01.0, using defaults\n"); printk_debug("ERROR - could not find PCI 1:01.0, using defaults\n");
bus_8131_1 = 2; bus_8131_1 = 2;
} }
/* 8131-2 */ /* 8131-2 */
dev = dev_find_slot(0, PCI_DEVFN(0x02,0)); dev = dev_find_slot(1, PCI_DEVFN(0x02,0));
if (dev) { if (dev) {
bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
} else { } else {
printk_debug("ERROR - could not find PCI 0:02.0, using defaults\n"); printk_debug("ERROR - could not find PCI 1:02.0, using defaults\n");
bus_8131_2 = 3; bus_8131_2 = 3;
} }
} }
@ -85,14 +85,14 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
device_t dev; device_t dev;
uint32_t base; uint32_t base;
/* 8131-1 apic #3 */ /* 8131-1 apic #3 */
dev = dev_find_slot(0, PCI_DEVFN(0x01,1)); dev = dev_find_slot(1, PCI_DEVFN(0x01,1));
if (dev) { if (dev) {
base = pci_read_config32(dev, PCI_BASE_ADDRESS_0); base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
base &= PCI_BASE_ADDRESS_MEM_MASK; base &= PCI_BASE_ADDRESS_MEM_MASK;
smp_write_ioapic(mc, 0x03, 0x11, base); smp_write_ioapic(mc, 0x03, 0x11, base);
} }
/* 8131-2 apic #4 */ /* 8131-2 apic #4 */
dev = dev_find_slot(0, PCI_DEVFN(0x02,1)); dev = dev_find_slot(1, PCI_DEVFN(0x02,1));
if (dev) { if (dev) {
base = pci_read_config32(dev, PCI_BASE_ADDRESS_0); base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
base &= PCI_BASE_ADDRESS_MEM_MASK; base &= PCI_BASE_ADDRESS_MEM_MASK;