soc/intel: Fix MCFG end bus number

The ACPI MCFG table is generated with a static end bus number of 255,
which expects that the reserved range in E820 is 256MB.  However the
actual MCFG range is configurable with Kconfig, so these two values
may not match when the OS tries to determine the range:

PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0xe0000000-0xefffffff] (base 0xe0000000)
PCI: MMCONFIG 0000 [bus 00-3f] at [mem 0xe0000000-0xe3ffffff] (base 0xe0000000) (size reduced!)
acpi PNP0A08:00: [Firmware Info]: MMCONFIG for domain 0000 [bus 00-3f] only partially covers this bridge

Instead of forcing the end bus number to be 255 use the Kconfig value
to set it based on the current configuration.

Tested on a fizz device to ensure that the kernel no longer complains:

PCI: MMCONFIG for domain 0000 [bus 00-3f] at [mem 0xe0000000-0xe3ffffff] (base 0xe0000000)

Change-Id: I999ea9b72b9deba5f27dd692faa0408427a0bf89
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/24974
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/common/block/acpi/acpi.c

@@ -36,7 +36,7 @@ unsigned long acpi_fill_mcfg(unsigned long current)
 	/* PCI Segment Group 0, Start Bus Number 0, End Bus Number is 255 */
 	current += acpi_create_mcfg_mmconfig((void *)current,
 					     CONFIG_MMCONF_BASE_ADDRESS, 0, 0,
-					     255);
+					     (CONFIG_SA_PCIEX_LENGTH >> 20) - 1);
 	return current;
 }
 

src/soc/intel/skylake/acpi.c

@@ -210,7 +210,8 @@ static void acpi_create_gnvs(global_nvs_t *gnvs)
 unsigned long acpi_fill_mcfg(unsigned long current)
 {
 	current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current,
-					     MCFG_BASE_ADDRESS, 0, 0, 255);
+					     MCFG_BASE_ADDRESS, 0, 0,
+					     (CONFIG_SA_PCIEX_LENGTH >> 20) - 1);
 	return current;
 }