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cpu/intel/haswell: Only change the slow ramp rate for ULT CPUs 

On my system (Pentium G3258, ASRock H81M-HDS), changing the the slow
ramp rate during `initialize_vr_config()` results in the following
exception, causing the system to hang.

	CPU Index 0 - APIC 0 Unexpected Exception:13 @ 10:7f7a3736 - Halting
	Code: 0 eflags: 00010006 cr2: 00000000
	eax: 00262626 ebx: 00140000 ecx: 00000603 edx: 00360000
	edi: 00000007 esi: 00262626 ebp: 7f7c0fd8 esp: 7f7c0e90

So, only change this setting for Haswell ULT CPUs, as suggested by the
BIOS Writer's guide.

Change-Id: I79b10139295741d298ac6c77c4f7272ac151ad90
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/29384
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Tristan Corrick 2018-10-31 02:27:12 +13:00 committed by Nico Huber
parent ba8ead817d
commit fdf907e440
1 changed files with 5 additions and 3 deletions
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8
src/cpu/intel/haswell/haswell_init.c
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@ -333,9 +333,11 @@ static void initialize_vr_config(void)
msr.hi &= ~(1 << (51 - 32));
/* Enable decay mode on C-state entry. */
msr.hi |= (1 << (52 - 32));
/* Set the slow ramp rate to be fast ramp rate / 4 */
msr.hi &= ~(0x3 << (53 - 32));
msr.hi |= (0x01 << (53 - 32));
if (haswell_is_ult()) {
/* Set the slow ramp rate to be fast ramp rate / 4 */
msr.hi &= ~(0x3 << (53 - 32));
msr.hi |= (0x01 << (53 - 32));
}
/* Set MIN_VID (31:24) to allow CPU to have full control. */
msr.lo &= ~0xff000000;
wrmsr(MSR_VR_MISC_CONFIG, msr);