northbridge/intel: Rename ram_calc.c to memmap.c

Use a name consistent with the more recent soc/intel.

Change-Id: Ie69583f28f384eb49517203e1c3867f27e6272de
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Kyösti Mälkki 2019-08-03 21:28:40 +03:00
parent e119d86ca8
commit fe481eb3e5
16 changed files with 24 additions and 24 deletions

View File

@ -25,18 +25,18 @@ romstage-y += pcie.c
romstage-y += thermal.c
romstage-y += igd.c
romstage-y += pm.c
romstage-y += ram_calc.c
romstage-y += memmap.c
romstage-y += iommu.c
romstage-y += romstage.c
ramstage-y += acpi.c
ramstage-y += ram_calc.c
ramstage-y += memmap.c
ramstage-y += northbridge.c
ramstage-y += gma.c
smm-y += ../../../cpu/x86/lapic/apic_timer.c
postcar-y += ram_calc.c
postcar-y += memmap.c
endif

View File

@ -17,14 +17,14 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_HASWELL),y)
bootblock-y += bootblock.c
ramstage-y += ram_calc.c
ramstage-y += memmap.c
ramstage-y += northbridge.c
ramstage-y += gma.c
ramstage-y += acpi.c
ramstage-y += minihd.c
romstage-y += ram_calc.c
romstage-y += memmap.c
romstage-y += raminit.c
romstage-y += early_init.c
romstage-y += report_platform.c
@ -37,6 +37,6 @@ mrc.bin-file := $(call strip_quotes,$(CONFIG_MRC_FILE))
mrc.bin-position := 0xfffa0000
mrc.bin-type := mrc
postcar-y += ram_calc.c
postcar-y += memmap.c
endif

View File

@ -17,12 +17,12 @@
ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I440BX),y)
ramstage-y += northbridge.c
ramstage-y += ram_calc.c
ramstage-y += memmap.c
romstage-y += raminit.c
romstage-$(CONFIG_DEBUG_RAM_SETUP) += debug.c
romstage-y += ram_calc.c
romstage-y += memmap.c
postcar-y += ram_calc.c
postcar-y += memmap.c
endif

View File

@ -15,12 +15,12 @@
ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I945),y)
ramstage-y += ram_calc.c
ramstage-y += memmap.c
ramstage-y += northbridge.c
ramstage-y += gma.c
ramstage-y += acpi.c
romstage-y += ram_calc.c
romstage-y += memmap.c
romstage-y += raminit.c
romstage-y += early_init.c
romstage-y += errata.c
@ -29,6 +29,6 @@ romstage-y += rcven.c
smm-y += udelay.c
postcar-y += ram_calc.c
postcar-y += memmap.c
endif

View File

@ -15,20 +15,20 @@
ifeq ($(CONFIG_NORTHBRIDGE_INTEL_NEHALEM),y)
ramstage-y += ram_calc.c
ramstage-y += memmap.c
ramstage-y += northbridge.c
ramstage-y += smi.c
ramstage-y += gma.c
ramstage-y += acpi.c
romstage-y += ram_calc.c
romstage-y += memmap.c
romstage-y += raminit.c
romstage-y += early_init.c
romstage-y += ../../../arch/x86/walkcbfs.S
smm-y += finalize.c
postcar-y += ram_calc.c
postcar-y += memmap.c
endif

View File

@ -19,16 +19,16 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_PINEVIEW),y)
bootblock-y += ../../../cpu/x86/early_reset.S
bootblock-y += bootblock.c
ramstage-y += ram_calc.c
ramstage-y += memmap.c
ramstage-y += northbridge.c
ramstage-y += gma.c
ramstage-y += acpi.c
romstage-y += romstage.c
romstage-y += ram_calc.c
romstage-y += memmap.c
romstage-y += raminit.c
romstage-y += early_init.c
postcar-y += ram_calc.c
postcar-y += memmap.c
endif

View File

@ -15,14 +15,14 @@
ifeq ($(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE),y)
ramstage-y += ram_calc.c
ramstage-y += memmap.c
ramstage-y += northbridge.c
ramstage-y += pcie.c
ramstage-y += gma.c
ramstage-y += acpi.c
romstage-y += ram_calc.c
romstage-y += memmap.c
ramstage-y += common.c
romstage-y += common.c
@ -48,6 +48,6 @@ romstage-y += ../../../arch/x86/walkcbfs.S
smm-y += finalize.c
postcar-y += ram_calc.c
postcar-y += memmap.c
endif

View File

@ -19,16 +19,16 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_X4X),y)
romstage-y += early_init.c
romstage-y += raminit.c
romstage-y += raminit_ddr23.c
romstage-y += ram_calc.c
romstage-y += memmap.c
romstage-y += rcven.c
romstage-y += raminit_tables.c
romstage-y += dq_dqs.c
ramstage-y += acpi.c
ramstage-y += ram_calc.c
ramstage-y += memmap.c
ramstage-y += gma.c
ramstage-y += northbridge.c
postcar-y += ram_calc.c
postcar-y += memmap.c
endif