mb/jetway: Get rid of whitespace before tab
Change-Id: Icc7d7fee38e41f4bfda685fd42bf504a788b440c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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@ -52,7 +52,7 @@ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigP
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static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr)
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{
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AGESA_STATUS Status;
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uint32_t FcnData;
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uint32_t FcnData;
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PCIe_SLOT_RESET_INFO *ResetInfo;
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uint32_t GpioMmioAddr;
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@ -72,7 +72,7 @@ Scope(\_GPE) { /* Start Scope GPE */
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Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
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Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
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}
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} /* End Scope GPE */
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} /* End Scope GPE */
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/* Contains the GPEs for USB overcurrent */
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#include "usb_oc.asl"
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@ -49,7 +49,7 @@ Method(\_PTS, 1) {
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/* On older chips, clear PciExpWakeDisEn */
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/*if (LLessEqual(\_SB.SBRI, 0x13)) {
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* Store(0,\_SB.PWDE)
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* Store(0,\_SB.PWDE)
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*}
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*/
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@ -10,7 +10,7 @@ chip northbridge/amd/amdfam10/root_complex
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chip northbridge/amd/amdfam10
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device pci 18.0 on # northbridge
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chip southbridge/amd/rs780
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device pci 0.0 on end # HT 0x9600
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device pci 0.0 on end # HT 0x9600
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device pci 1.0 on end # Internal Graphics P2P bridge 0x9602
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device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603
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device pci 3.0 on end # PCIE P2P bridge 0x960b
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@ -40,7 +40,7 @@ chip northbridge/amd/amdfam10/root_complex
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device pci 13.0 on end # USB
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device pci 13.1 on end # USB
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device pci 13.2 on end # USB
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device pci 14.0 on # SM
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device pci 14.0 on # SM
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chip drivers/generic/generic #dimm 0-0-0
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device i2c 50 on end
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end
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@ -239,9 +239,9 @@ DefinitionBlock (
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PWMK, 1,
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PWNS, 1,
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/* Offset(0x61), */ /* Options_1 */
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/* ,7, */
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/* R617,1, */
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/* Offset(0x61), */ /* Options_1 */
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/* ,7, */
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/* R617,1, */
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Offset(0x65), /* UsbPMControl */
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, 4,
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@ -837,7 +837,7 @@ DefinitionBlock (
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/* On older chips, clear PciExpWakeDisEn */
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/*if (LLessEqual(\_SB.SBRI, 0x13)) {
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* Store(0,\_SB.PWDE)
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* Store(0,\_SB.PWDE)
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*}
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*/
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@ -853,13 +853,13 @@ DefinitionBlock (
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* used, so it could be removed.
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*
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*
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* \_GTS OEM Going To Sleep method
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* \_GTS OEM Going To Sleep method
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*
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* Entry:
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* Arg0=The value of the sleeping state S1=1, S2=2
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* Entry:
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* Arg0=The value of the sleeping state S1=1, S2=2
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*
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* Exit:
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* -none-
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* Exit:
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* -none-
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*
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* Method(\_GTS, 1) {
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* DBGO("\\_GTS\n")
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@ -1026,7 +1026,7 @@ DefinitionBlock (
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/* PCIe HotPlug event */
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/* Method(_L0F) {
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* DBGO("\\_GPE\\_L0F\n")
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* DBGO("\\_GPE\\_L0F\n")
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* }
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*/
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@ -1049,19 +1049,19 @@ DefinitionBlock (
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/* GPM0 SCI event - Moved to USB.asl */
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/* Method(_L13) {
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* DBGO("\\_GPE\\_L13\n")
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* DBGO("\\_GPE\\_L13\n")
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* }
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*/
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/* GPM1 SCI event - Moved to USB.asl */
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/* Method(_L14) {
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* DBGO("\\_GPE\\_L14\n")
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* DBGO("\\_GPE\\_L14\n")
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* }
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*/
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/* GPM2 SCI event - Moved to USB.asl */
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/* Method(_L15) {
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* DBGO("\\_GPE\\_L15\n")
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* DBGO("\\_GPE\\_L15\n")
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* }
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*/
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@ -1073,7 +1073,7 @@ DefinitionBlock (
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/* GPM8 SCI event - Moved to USB.asl */
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/* Method(_L17) {
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* DBGO("\\_GPE\\_L17\n")
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* DBGO("\\_GPE\\_L17\n")
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* }
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*/
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@ -1090,7 +1090,7 @@ DefinitionBlock (
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/* GPM4 SCI event - Moved to USB.asl */
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/* Method(_L19) {
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* DBGO("\\_GPE\\_L19\n")
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* DBGO("\\_GPE\\_L19\n")
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* }
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*/
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@ -1121,7 +1121,7 @@ DefinitionBlock (
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/* GPIO2 or GPIO66 SCI event */
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/* Method(_L1E) {
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* DBGO("\\_GPE\\_L1E\n")
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* DBGO("\\_GPE\\_L1E\n")
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* }
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*/
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@ -1131,7 +1131,7 @@ DefinitionBlock (
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* }
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*/
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} /* End Scope GPE */
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} /* End Scope GPE */
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#include "acpi/usb.asl"
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@ -1520,7 +1520,7 @@ DefinitionBlock (
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)
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Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
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Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */
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Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */
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Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */
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Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */
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@ -1634,7 +1634,7 @@ DefinitionBlock (
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/* On older chips, clear PciExpWakeDisEn */
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/*if (LLessEqual(\SBRI, 0x13)) {
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* Store(0,\PWDE)
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* Store(0,\PWDE)
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* }
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*/
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} /* End Method(_SB._INI) */
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