util/inteltool: ahci: add Sunrise Point config and SIR registers
This adds the Sunrise Point AHCI config and SIR registers from doc#332691-003EN. Change-Id: Id4a462d625194a6ccfdb88fb415d5eb278f2900a Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39506 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -34,6 +34,53 @@ static const char *port_ctl_regs[] = {
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"PxFBS", "PxDEVSLP", "Reserved"
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};
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static const io_register_t sunrise_ahci_cfg_registers[] = {
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{0x0, 4, "ID"},
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{0x4, 2, "CMD"},
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{0x6, 2, "STS"},
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{0x8, 1, "RID"},
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{0x9, 1, "PI"},
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{0xa, 2, "CC"},
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{0xc, 1, "CLS"},
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{0xd, 1, "MLT"},
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{0xe, 1, "HTYPE"},
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{0x10, 4, "MXTBA"},
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{0x14, 4, "MXPBA"},
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{0x20, 4, "AIDPBA"},
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{0x24, 4, "ABAR"},
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{0x2c, 4, "SS"},
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{0x34, 1, "CAP"},
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{0x3c, 2, "INTR"},
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{0x70, 2, "PID"},
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{0x72, 2, "PC"},
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{0x74, 2, "PMCS"},
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{0x80, 2, "MID"},
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{0x82, 2, "MC"},
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{0x84, 4, "MA"},
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{0x88, 2, "MD"},
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{0x90, 4, "MAP"},
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{0x94, 4, "PCS"},
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{0x9c, 4, "SATAGC"},
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{0xa0, 1, "SIRI"},
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{0xa4, 4, "SIRD"},
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{0xa8, 4, "SATACR0"},
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{0xac, 4, "SATACR1"},
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{0xc0, 4, "SP"},
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{0xd0, 2, "MXID"},
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{0xd2, 2, "MXC"},
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{0xd4, 4, "MXT"},
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{0xd8, 4, "MXP"},
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{0xe0, 4, "BFCS"},
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{0xe4, 4, "BFTD1"},
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{0xe8, 4, "BFTD2"},
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};
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static const io_register_t sunrise_ahci_sir_registers[] = {
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{0x80, 4, "SQUELCH"},
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{0x90, 4, "SATA_MPHY_PG"},
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{0xa4, 4, "OOBRETR"},
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};
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#define NUM_GHC (sizeof(ghc_regs)/sizeof(ghc_regs[0]))
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#define NUM_PORTCTL (sizeof(port_ctl_regs)/sizeof(port_ctl_regs[0]))
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@ -76,6 +123,11 @@ int print_ahci(struct pci_dev *ahci)
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case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_SATA:
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case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SATA:
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ahci_registers_size = 0x800;
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ahci_sir_offset = 0xa0;
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ahci_cfg_registers = sunrise_ahci_cfg_registers;
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ahci_cfg_registers_size = ARRAY_SIZE(sunrise_ahci_cfg_registers);
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ahci_sir_registers = sunrise_ahci_sir_registers;
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ahci_sir_registers_size = ARRAY_SIZE(sunrise_ahci_sir_registers);
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break;
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default:
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ahci_registers_size = 0x400;
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