google/glados: enable VMX for all variants
Explicitly enable VMX, as some OSes (eg, Windows) need VMX feature enabled and locked in order to fully support virtualization Test: boot Windows 10 on google/chell, verify OS reports virtualization enabled Change-Id: I53ff575755a9ca376dbf953db96191c17bf57f5f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27549 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
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@ -44,6 +44,7 @@ chip soc/intel/skylake
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register "PmConfigSlpSusMinAssert" = "3" # 4s
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register "PmConfigSlpSusMinAssert" = "3" # 4s
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register "PmConfigSlpAMinAssert" = "3" # 2s
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register "PmConfigSlpAMinAssert" = "3" # 2s
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register "PmTimerDisabled" = "1"
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register "PmTimerDisabled" = "1"
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register "VmxEnable" = "1"
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register "pirqa_routing" = "PCH_IRQ11"
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register "pirqa_routing" = "PCH_IRQ11"
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register "pirqb_routing" = "PCH_IRQ10"
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register "pirqb_routing" = "PCH_IRQ10"
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@ -54,6 +54,7 @@ chip soc/intel/skylake
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register "PmConfigSlpSusMinAssert" = "1" # 500ms
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register "PmConfigSlpSusMinAssert" = "1" # 500ms
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register "PmConfigSlpAMinAssert" = "3" # 2s
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register "PmConfigSlpAMinAssert" = "3" # 2s
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register "PmTimerDisabled" = "1"
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register "PmTimerDisabled" = "1"
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register "VmxEnable" = "1"
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# TCC offset
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# TCC offset
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register "tcc_offset" = "10"
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register "tcc_offset" = "10"
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@ -54,6 +54,7 @@ chip soc/intel/skylake
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register "PmConfigSlpSusMinAssert" = "1" # 500ms
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register "PmConfigSlpSusMinAssert" = "1" # 500ms
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register "PmConfigSlpAMinAssert" = "3" # 2s
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register "PmConfigSlpAMinAssert" = "3" # 2s
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register "PmTimerDisabled" = "1"
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register "PmTimerDisabled" = "1"
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register "VmxEnable" = "1"
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register "pirqa_routing" = "PCH_IRQ11"
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register "pirqa_routing" = "PCH_IRQ11"
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register "pirqb_routing" = "PCH_IRQ10"
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register "pirqb_routing" = "PCH_IRQ10"
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@ -54,6 +54,7 @@ chip soc/intel/skylake
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register "PmConfigSlpSusMinAssert" = "1" # 500ms
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register "PmConfigSlpSusMinAssert" = "1" # 500ms
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register "PmConfigSlpAMinAssert" = "3" # 2s
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register "PmConfigSlpAMinAssert" = "3" # 2s
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register "PmTimerDisabled" = "1"
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register "PmTimerDisabled" = "1"
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register "VmxEnable" = "1"
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register "pirqa_routing" = "PCH_IRQ11"
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register "pirqa_routing" = "PCH_IRQ11"
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register "pirqb_routing" = "PCH_IRQ10"
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register "pirqb_routing" = "PCH_IRQ10"
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@ -54,6 +54,7 @@ chip soc/intel/skylake
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register "PmConfigSlpSusMinAssert" = "1" # 500ms
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register "PmConfigSlpSusMinAssert" = "1" # 500ms
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register "PmConfigSlpAMinAssert" = "3" # 2s
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register "PmConfigSlpAMinAssert" = "3" # 2s
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register "PmTimerDisabled" = "1"
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register "PmTimerDisabled" = "1"
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register "VmxEnable" = "1"
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register "pirqa_routing" = "PCH_IRQ11"
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register "pirqa_routing" = "PCH_IRQ11"
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register "pirqb_routing" = "PCH_IRQ10"
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register "pirqb_routing" = "PCH_IRQ10"
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@ -42,6 +42,7 @@ chip soc/intel/skylake
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register "PmConfigSlpSusMinAssert" = "3" # 4s
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register "PmConfigSlpSusMinAssert" = "3" # 4s
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register "PmConfigSlpAMinAssert" = "3" # 2s
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register "PmConfigSlpAMinAssert" = "3" # 2s
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register "PmTimerDisabled" = "1"
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register "PmTimerDisabled" = "1"
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register "VmxEnable" = "1"
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register "pirqa_routing" = "PCH_IRQ11"
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register "pirqa_routing" = "PCH_IRQ11"
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register "pirqb_routing" = "PCH_IRQ10"
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register "pirqb_routing" = "PCH_IRQ10"
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@ -44,6 +44,7 @@ chip soc/intel/skylake
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register "PmConfigSlpSusMinAssert" = "3" # 4s
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register "PmConfigSlpSusMinAssert" = "3" # 4s
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register "PmConfigSlpAMinAssert" = "3" # 2s
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register "PmConfigSlpAMinAssert" = "3" # 2s
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register "PmTimerDisabled" = "1"
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register "PmTimerDisabled" = "1"
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register "VmxEnable" = "1"
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register "pirqa_routing" = "PCH_IRQ11"
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register "pirqa_routing" = "PCH_IRQ11"
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register "pirqb_routing" = "PCH_IRQ10"
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register "pirqb_routing" = "PCH_IRQ10"
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