mb/google/volteer: Add gpio-keys ACPI node for PENH

Use gpio_keys driver to add ACPI node for pen eject event.  Also
setting gpio wake pin for wake events.

Removal and insertion (both edges) triggers IRQ and only removal is a
wake event (rising edge).

Adding for both Volteer and Volteer2 variants.

BUG=b:146083964
BRANCH=None
TEST=tested on a Volteer

Change-Id: Ida3217a5b156320856ce3302c2623eba2230f28d
Signed-off-by: Alex Levin <levinale@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43764
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Alex Levin 2020-07-23 11:55:12 -07:00 committed by Patrick Georgi
parent 061f0d205b
commit ff1c5bec03
4 changed files with 29 additions and 2 deletions

View File

@ -1,6 +1,7 @@
config BOARD_GOOGLE_BASEBOARD_VOLTEER
def_bool n
select BOARD_ROMSIZE_KB_32768
select DRIVERS_GENERIC_GPIO_KEYS
select DRIVERS_GENERIC_MAX98357A
select DRIVERS_I2C_GENERIC
select DRIVERS_I2C_HID

View File

@ -30,7 +30,7 @@ static const struct pad_config override_gpio_table[] = {
PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1),
/* B3 : CPU_GP2 ==> PEN_DET_ODL */
PAD_CFG_GPI(GPP_B3, NONE, DEEP),
PAD_CFG_GPI_GPIO_DRIVER(GPP_B3, NONE, PLTRST),
/* B5 : ISH_I2C0_CVF_SDA */
PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
/* B6 : ISH_I2C0_CVF_SCL */
@ -98,7 +98,7 @@ static const struct pad_config override_gpio_table[] = {
PAD_CFG_GPO(GPP_D18, 1, DEEP),
/* E1 : SPI1_IO2 ==> PEN_DET_ODL */
PAD_CFG_GPI_SCI_LOW(GPP_E1, NONE, DEEP, EDGE_SINGLE),
PAD_CFG_GPI_SCI(GPP_E1, NONE, DEEP, EDGE_SINGLE, NONE),
/* E2 : SPI1_IO3 ==> WLAN_PCIE_WAKE_ODL */
PAD_CFG_GPI(GPP_E2, NONE, DEEP),
/* E3 : CPU_GP0 ==> USI_REPORT_EN */

View File

@ -68,6 +68,19 @@ chip soc/intel/tigerlake
register "hid_desc_reg_offset" = "0x01"
device i2c 10 on end
end
chip drivers/generic/gpio_keys
register "name" = ""PENH""
# GPP_B3 is the IRQ source, and GPP_E1 is the wake source
register "gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_B3)"
register "key.wake_gpe" = "GPE0_DW2_01"
register "key.wakeup_route" = "WAKEUP_ROUTE_SCI"
register "key.wakeup_event_action" = "EV_ACT_DEASSERTED"
register "key.dev_name" = ""EJCT""
register "key.linux_code" = "SW_PEN_INSERTED"
register "key.linux_input_type" = "EV_SW"
register "key.label" = ""pen_eject""
device generic 0 on end
end
end # I2C1 0xA0E9
device pci 15.2 on
chip drivers/i2c/sx9310

View File

@ -67,6 +67,19 @@ chip soc/intel/tigerlake
register "hid_desc_reg_offset" = "0x01"
device i2c 10 on end
end
chip drivers/generic/gpio_keys
register "name" = ""PENH""
# GPP_B3 is the IRQ source, and GPP_E1 is the wake source
register "gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_B3)"
register "key.wake_gpe" = "GPE0_DW2_01"
register "key.wakeup_route" = "WAKEUP_ROUTE_SCI"
register "key.wakeup_event_action" = "EV_ACT_DEASSERTED"
register "key.dev_name" = ""EJCT""
register "key.linux_code" = "SW_PEN_INSERTED"
register "key.linux_input_type" = "EV_SW"
register "key.label" = ""pen_eject""
device generic 0 on end
end
end # I2C1 0xA0E9
device pci 15.2 on
chip drivers/i2c/sx9310