sb/intel/bd82x6x: Reduce function-disable mess

Most affected boards set the function disabled (FD) register to an
arbitrary state dumped from systems running the vendor BIOS. This
makes it impossible to enable the devices in devicetree and a pretty
big mess of course because nobody cared to keep the register in sync
with the devicetree.

To get completely rid of most of the writes to FD, move setting of
PCH_DISABLE_ALWAYS into the southbridge code where it belongs.

Change-Id: Ia2a507cbcdf218d09738e2e16f0d3ad1dcf57b8b
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/23255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hal Martin <hal.martin+coreboot@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Bill XIE <persmule@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

src/mainboard/apple/macbookair4_2/early_southbridge.c

@@ -41,12 +41,10 @@ void pch_enable_lpc(void)
 	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x80000000);
 }
 
-void rcba_config(void)
+void mainboard_rcba_config(void)
 {
 	/* Disable devices.  */
 	RCBA32(0x3414) = 0x00000020;
-	RCBA32(0x3418) = 0x1ffc0ee3;
-
 }
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 0, -1 },

src/mainboard/asrock/b75pro3-m/romstage.c

@@ -27,9 +27,8 @@ void pch_enable_lpc(void)
 	pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0000);
 }
 
-void rcba_config(void)
+void mainboard_rcba_config(void)
 {
-	RCBA32(FD) = PCH_DISABLE_ALWAYS | 0x10001fe0;
 }
 
 const struct southbridge_usb_port mainboard_usb_ports[] = {

src/mainboard/compulab/intense_pc/romstage.c

@@ -47,12 +47,9 @@ void pch_enable_lpc(void)
 #endif
 }
 
-void rcba_config(void)
+void mainboard_rcba_config(void)
 {
-	/* Disable devices. */
 	RCBA32(0x3414) = 0x00000000;
-	RCBA32(0x3418) = 0x16e81fe3;
-
 }
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 1, 0 },

src/mainboard/gigabyte/ga-b75m-d3h/romstage.c

@@ -61,7 +61,7 @@ static void it8728f_b75md3h_disable_reboot(pnp_devfn_t dev)
 	ite_reg_write(IT8728F_EC, 0x30, 0x01);
 }
 
-void rcba_config(void)
+void mainboard_rcba_config(void)
 {
 /*
 	pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
@@ -131,9 +131,6 @@ void rcba_config(void)
 	RCBA32(0x3844) = 0x0000e5e4;
 	RCBA32(0x3848) = 0x0000000e;
 */
-	/* Disable unused devices (board specific) */
-	RCBA32(FD) = 0x17ee1fe1;
-
 	/* Enable HECI */
 	RCBA32(FD2) &= ~0x2;
 }

src/mainboard/gigabyte/ga-b75m-d3v/romstage.c

@@ -61,11 +61,8 @@ static void it8728f_b75md3v_disable_reboot(pnp_devfn_t dev)
 	ite_reg_write(IT8728F_EC, 0x30, 0x01);
 }
 
-void rcba_config(void)
+void mainboard_rcba_config(void)
 {
-	/* Disable unused devices (board specific) */
-	RCBA32(FD) = 0x17ee1fe1;
-
 	/* Enable HECI */
 	RCBA32(FD2) &= ~0x2;
 }

src/mainboard/google/butterfly/romstage.c

@@ -53,7 +53,7 @@ void pch_enable_lpc(void)
 
 }
 
-void rcba_config(void)
+void mainboard_rcba_config(void)
 {
 	u32 reg32;
 
@@ -101,7 +101,6 @@ void rcba_config(void)
 
 	/* Disable unused devices (board specific) */
 	reg32 = RCBA32(FD);
-	reg32 |= PCH_DISABLE_ALWAYS;
 	/* Disable PCI bridge so MRC does not probe this bus */
 	reg32 |= PCH_DISABLE_P2P;
 	RCBA32(FD) = reg32;

src/mainboard/google/link/romstage.c

@@ -66,10 +66,8 @@ void pch_enable_lpc(void)
 	pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, config->gen4_dec);
 }
 
-void rcba_config(void)
+void mainboard_rcba_config(void)
 {
-	u32 reg32;
-
 	/*
 	 *             GFX    INTA -> PIRQA (MSI)
 	 * D28IP_P3IP  WLAN   INTA -> PIRQB
@@ -108,11 +106,6 @@ void rcba_config(void)
 	RCBA16(OIC) = 0x0100;
 	/* PCH BWG says to read back the IOAPIC enable register */
 	(void) RCBA16(OIC);
-
-	/* Disable unused devices (board specific) */
-	reg32 = RCBA32(FD);
-	reg32 |= PCH_DISABLE_ALWAYS;
-	RCBA32(FD) = reg32;
 }
 
 static uint8_t *locate_spd(void)

src/mainboard/google/parrot/romstage.c

@@ -51,7 +51,7 @@ void pch_enable_lpc(void)
 	pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, (68 & ~3) | 0x00040001);
 }
 
-void rcba_config(void)
+void mainboard_rcba_config(void)
 {
 	u32 reg32;
 
@@ -100,7 +100,6 @@ void rcba_config(void)
 
 	/* Disable unused devices (board specific) */
 	reg32 = RCBA32(FD);
-	reg32 |= PCH_DISABLE_ALWAYS;
 	/* Disable PCI bridge so MRC does not probe this bus */
 	reg32 |= PCH_DISABLE_P2P;
 	RCBA32(FD) = reg32;

src/mainboard/google/stout/romstage.c

@@ -57,7 +57,7 @@ void pch_enable_lpc(void)
 	pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, (0x68 | 0x40001));
 }
 
-void rcba_config(void)
+void mainboard_rcba_config(void)
 {
 	u32 reg32;
 
@@ -106,7 +106,6 @@ void rcba_config(void)
 
 	/* Disable unused devices (board specific) */
 	reg32 = RCBA32(FD);
-	reg32 |= PCH_DISABLE_ALWAYS;
 	/* Disable PCI bridge so MRC does not probe this bus */
 	reg32 |= PCH_DISABLE_P2P;
 	RCBA32(FD) = reg32;

src/mainboard/hp/2570p/romstage.c

@@ -32,9 +32,8 @@ void pch_enable_lpc(void)
 	pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201);
 }
 
-void rcba_config(void)
+void mainboard_rcba_config(void)
 {
-	RCBA32(FD) = PCH_DISABLE_ALWAYS | 0x10001fe0;
 }
 
 const struct southbridge_usb_port mainboard_usb_ports[] = {

src/mainboard/hp/2760p/romstage.c

@@ -31,9 +31,8 @@ void pch_enable_lpc(void)
 	pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201);
 }
 
-void rcba_config(void)
+void mainboard_rcba_config(void)
 {
-	RCBA32(FD) = PCH_DISABLE_ALWAYS | 0x10001fe0;
 }
 
 const struct southbridge_usb_port mainboard_usb_ports[] = {

src/mainboard/hp/8460p/romstage.c

@@ -38,9 +38,8 @@ void pch_enable_lpc(void)
 	pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201);
 }
 
-void rcba_config(void)
+void mainboard_rcba_config(void)
 {
-	RCBA32(FD) = PCH_DISABLE_ALWAYS | 0x10001fe0;
 }
 
 const struct southbridge_usb_port mainboard_usb_ports[] = {

src/mainboard/hp/8470p/romstage.c

@@ -37,9 +37,8 @@ void pch_enable_lpc(void)
 	pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201);
 }
 
-void rcba_config(void)
+void mainboard_rcba_config(void)
 {
-	RCBA32(FD) = PCH_DISABLE_ALWAYS | 0x10001fe0;
 }
 
 const struct southbridge_usb_port mainboard_usb_ports[] = {

src/mainboard/hp/revolve_810_g1/romstage.c

@@ -37,13 +37,11 @@ void pch_enable_lpc(void)
 	pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201);
 }
 
-void rcba_config(void)
+void mainboard_rcba_config(void)
 {
-	/* Disable devices.  */
 	RCBA32(BUC) = 0x00000000;
-	RCBA32(FD) = 0x17f21feb;
-
 }
+
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 1, 0 },
 	{ 1, 0, 0 },

src/mainboard/intel/dcp847ske/early_southbridge.c

@@ -41,10 +41,10 @@ void pch_enable_lpc(void)
 	pci_write_config32(PCI_DEV(0, 0x1f, 0), LPC_GEN1_DEC, 0x00fc0a01);
 }
 
-void rcba_config(void)
+void mainboard_rcba_config(void)
 {
 	/* Disable devices */
-	RCBA32(FD) |= PCH_DISABLE_ALWAYS | PCH_DISABLE_P2P | PCH_DISABLE_XHCI;
+	RCBA32(FD) |= PCH_DISABLE_P2P | PCH_DISABLE_XHCI;
 
 #if IS_ENABLED(CONFIG_USE_NATIVE_RAMINIT)
 	/* Enable Gigabit Ethernet */

src/mainboard/intel/emeraldlake2/romstage.c

@@ -63,16 +63,9 @@ void pch_enable_lpc(void)
 	}
 }
 
-void rcba_config(void)
+void mainboard_rcba_config(void)
 {
-	u32 reg32;
-
 	southbridge_configure_default_intmap();
-
-	/* Disable unused devices (board specific) */
-	reg32 = RCBA32(FD);
-	reg32 |= PCH_DISABLE_ALWAYS;
-	RCBA32(FD) = reg32;
 }
 
 void mainboard_config_superio(void)

src/mainboard/kontron/ktqm77/romstage.c

@@ -51,13 +51,12 @@ void pch_enable_lpc(void)
 			   COMA_LPC_EN | COMB_LPC_EN);
 }
 
-void rcba_config(void)
+void mainboard_rcba_config(void)
 {
 	u32 reg32;
 
 	/* Disable unused devices (board specific) */
 	reg32 = RCBA32(FD);
-	reg32 |= PCH_DISABLE_ALWAYS;
 	/* Disable PCI bridge so MRC does not probe this bus */
 	reg32 |= PCH_DISABLE_P2P;
 	RCBA32(FD) = reg32;

src/mainboard/lenovo/l520/romstage.c

@@ -32,12 +32,9 @@ void pch_enable_lpc(void)
 	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000000);
 }
 
-void rcba_config(void)
+void mainboard_rcba_config(void)
 {
-	/* Disable devices.  */
 	RCBA32(0x3414) = 0x00000000;
-	RCBA32(0x3418) = 0x00000000;
-
 }
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 0, -1 },

src/mainboard/lenovo/s230u/romstage.c

@@ -55,12 +55,10 @@ void pch_enable_lpc(void)
 		ec_mm_set_bit(0x3b, 4);
 }
 
-void rcba_config(void)
+void mainboard_rcba_config(void)
 {
 	/* Disable devices.  */
 	RCBA32(0x3414) = 0x00000020;
-	RCBA32(0x3418) = 0x17f41fe3;
-
 }
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 1, 0 },

src/mainboard/lenovo/t420/romstage.c

@@ -60,12 +60,11 @@ void pch_enable_lpc(void)
 	pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
 }
 
-void rcba_config(void)
+void mainboard_rcba_config(void)
 {
-	/* Disable unused devices (board specific) */
-	RCBA32(FD) = 0x1ea51fe3;
 	RCBA32(BUC) = 0;
 }
+
 // OC3 set in bios to port 2-7, OC7 set in bios to port 10-13
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 1,  0 }, /* P0: system port 4, OC0 */

src/mainboard/lenovo/t420s/romstage.c

@@ -62,10 +62,8 @@ void pch_enable_lpc(void)
 	pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
 }
 
-void rcba_config(void)
+void mainboard_rcba_config(void)
 {
-	/* Disable unused devices (board specific) */
-	RCBA32(FD) = 0x1eb51fe3;
 	RCBA32(BUC) = 0;
 }
 

src/mainboard/lenovo/t430/romstage.c

@@ -57,11 +57,8 @@ void pch_enable_lpc(void)
 			   (0x0c << 16) | EC_LENOVO_PMH7_BASE | 1);
 }
 
-void rcba_config(void)
+void mainboard_rcba_config(void)
 {
-	/* Disable unused devices (board specific, reserved only).
-	 * FIXME: Test if reserved bits are read only. */
-	RCBA32(FD) = PCH_DISABLE_ALWAYS | 0x10001fe0;
 }
 
 /* FIXME: used T530 values here */

src/mainboard/lenovo/t430s/romstage.c

@@ -36,10 +36,8 @@ void pch_enable_lpc(void)
 	pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
 }
 
-void rcba_config(void)
+void mainboard_rcba_config(void)
 {
-	/* Disable unused devices (board specific) */
-	RCBA32(FD) = 0x17e81fe3;
 	RCBA32(BUC) = 0;
 }
 

src/mainboard/lenovo/t520/romstage.c

@@ -76,10 +76,8 @@ void pch_enable_lpc(void)
 	pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
 }
 
-void rcba_config(void)
+void mainboard_rcba_config(void)
 {
-	/* Disable unused devices (board specific) */
-	RCBA32(FD) = 0x1ee51fe3;
 	RCBA32(BUC) = 0;
 }
 

src/mainboard/lenovo/t530/romstage.c

@@ -64,10 +64,8 @@ void pch_enable_lpc(void)
 	pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
 }
 
-void rcba_config(void)
+void mainboard_rcba_config(void)
 {
-	/* Disable unused devices (board specific) */
-	RCBA32(FD) = 0x17f81fe3;
 	RCBA32(BUC) = 0;
 }
 

src/mainboard/lenovo/x131e/romstage.c

@@ -33,9 +33,8 @@ void pch_enable_lpc(void)
 	pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x000c06a1);
 }
 
-void rcba_config(void)
+void mainboard_rcba_config(void)
 {
-	RCBA32(FD) |= PCH_DISABLE_ALWAYS;
 }
 
 const struct southbridge_usb_port mainboard_usb_ports[] = {

src/mainboard/lenovo/x1_carbon_gen1/romstage.c

@@ -86,7 +86,7 @@ static uint8_t *get_spd_data(int spd_index)
 	return spd_file + spd_index * 256;
 }
 
-void rcba_config(void)
+void mainboard_rcba_config(void)
 {
 }
 

src/mainboard/lenovo/x220/romstage.c

@@ -47,10 +47,8 @@ void pch_enable_lpc(void)
 	pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
 }
 
-void rcba_config(void)
+void mainboard_rcba_config(void)
 {
-	/* Disable unused devices (board specific) */
-	RCBA32(FD) = 0x1fa41fe3;
 	RCBA32(BUC) = 0;
 }
 

src/mainboard/lenovo/x230/romstage.c

@@ -50,10 +50,8 @@ void pch_enable_lpc(void)
 	pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
 }
 
-void rcba_config(void)
+void mainboard_rcba_config(void)
 {
-	/* Disable unused devices (board specific) */
-	RCBA32(FD) = 0x17f81fe3;
 	RCBA32(BUC) = 0;
 }
 

src/mainboard/roda/rv11/romstage.c

@@ -16,13 +16,12 @@
 #include <northbridge/intel/sandybridge/sandybridge.h>
 #include <southbridge/intel/bd82x6x/pch.h>
 
-void rcba_config(void)
+void mainboard_rcba_config(void)
 {
 	u32 reg32;
 
 	/* Disable unused devices (board specific) */
 	reg32 = RCBA32(FD);
-	reg32 |= PCH_DISABLE_ALWAYS;
 	/* Disable PCI bridge so MRC does not probe this bus */
 	reg32 |= PCH_DISABLE_P2P;
 	RCBA32(FD) = reg32;

src/mainboard/samsung/lumpy/romstage.c

@@ -63,10 +63,8 @@ void pch_enable_lpc(void)
 #endif
 }
 
-void rcba_config(void)
+void mainboard_rcba_config(void)
 {
-	u32 reg32;
-
 	/*
 	 *             GFX    INTA -> PIRQA (MSI)
 	 * D28IP_P1IP  WLAN   INTA -> PIRQB
@@ -107,11 +105,6 @@ void rcba_config(void)
 	RCBA16(OIC) = 0x0100;
 	/* PCH BWG says to read back the IOAPIC enable register */
 	(void) RCBA16(OIC);
-
-	/* Disable unused devices (board specific) */
-	reg32 = RCBA32(FD);
-	reg32 |= PCH_DISABLE_ALWAYS;
-	RCBA32(FD) = reg32;
 }
 
 static const uint8_t *locate_spd(void)

src/mainboard/samsung/stumpy/romstage.c

@@ -75,10 +75,8 @@ void pch_enable_lpc(void)
 #endif
 }
 
-void rcba_config(void)
+void mainboard_rcba_config(void)
 {
-	u32 reg32;
-
 	/*
 	 *             GFX    INTA -> PIRQA (MSI)
 	 * D28IP_P1IP  WLAN   INTA -> PIRQB
@@ -116,11 +114,6 @@ void rcba_config(void)
 	RCBA16(OIC) = 0x0100;
 	/* PCH BWG says to read back the IOAPIC enable register */
 	(void) RCBA16(OIC);
-
-	/* Disable unused devices (board specific) */
-	reg32 = RCBA32(FD);
-	reg32 |= PCH_DISABLE_ALWAYS;
-	RCBA32(FD) = reg32;
 }
 
 static void setup_sio_gpios(void)

src/mainboard/sapphire/pureplatinumh61/romstage.c

@@ -44,12 +44,10 @@ void pch_enable_lpc(void)
 	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x00010000);
 }
 
-void rcba_config(void)
+void mainboard_rcba_config(void)
 {
 	/* Disable devices.  */
 	RCBA32(0x3414) = 0x00000020;
-	RCBA32(0x3418) = 0x1fce1fe3;
-
 }
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 0, 0 },

src/northbridge/intel/sandybridge/romstage.c

@@ -110,7 +110,8 @@ void mainboard_romstage_entry(unsigned long bist)
 	post_code(0x3c);
 
 	southbridge_configure_default_intmap();
-	rcba_config();
+	southbridge_rcba_config();
+	mainboard_rcba_config();
 
 	post_code(0x3d);
 

src/northbridge/intel/sandybridge/sandybridge.h

@@ -220,7 +220,6 @@ void report_platform_info(void);
 
 #endif /* !__SMM__ */
 
-void rcba_config(void);
 void pch_enable_lpc(void);
 void mainboard_early_init(int s3resume);
 void mainboard_config_superio(void);

src/southbridge/intel/bd82x6x/early_rcba.c

@@ -63,3 +63,9 @@ southbridge_configure_default_intmap(void)
 	/* PCH BWG says to read back the IOAPIC enable register */
 	(void) RCBA16(OIC);
 }
+
+void
+southbridge_rcba_config(void)
+{
+	RCBA32(FD) = PCH_DISABLE_ALWAYS;
+}

src/southbridge/intel/bd82x6x/pch.h

@@ -85,6 +85,8 @@ int smbus_read_byte(unsigned device, unsigned address);
 int early_spi_read(u32 offset, u32 size, u8 *buffer);
 void early_thermal_init(void);
 void southbridge_configure_default_intmap(void);
+void southbridge_rcba_config(void);
+void mainboard_rcba_config(void);
 void early_pch_init_native(void);
 int southbridge_detect_s3_resume(void);