soc/intel/apollolake: Add support for LPSS I2C driver
Support the I2C interfaces on this SOC using the Intel common lpss_i2c driver. The controllers are supported in pre-ram environments by setting a temporary base address in bootblock and in ramstage using the naturally enumerated base address. The base speed of this controller is 133MHz and the SCL/SDA timing values that are reported to the OS are calculated using that clock. This was tested on a google/reef board doing I2C transactions to the trackpad both in verstage and in ramstage. Change-Id: I0a9d62cd1007caa95cdf4754f30c30aaff9f78f9 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15480 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Duncan Laurie
parent
02fcc88782
commit
ff8bce0a5f
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@ -41,8 +41,9 @@ config CPU_SPECIFIC_OPTIONS
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select RELOCATABLE_RAMSTAGE # Build fails if this is not selected
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select SMM_TSEG
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select SOC_INTEL_COMMON
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select SOC_INTEL_COMMON_SMI
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select SOC_INTEL_COMMON_ACPI
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select SOC_INTEL_COMMON_LPSS_I2C
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select SOC_INTEL_COMMON_SMI
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select SPI_FLASH
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select UDELAY_TSC
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select TSC_CONSTANT_RATE
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@ -96,6 +97,11 @@ config CPU_ADDR_BITS
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int
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default 36
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config SOC_INTEL_COMMON_LPSS_I2C_CLOCK_MHZ
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depends on SOC_INTEL_COMMON_LPSS_I2C
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int
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default 133
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config CONSOLE_UART_BASE_ADDRESS
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depends on CONSOLE_SERIAL
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hex "MMIO base address for UART"
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@ -23,6 +23,7 @@ bootblock-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
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romstage-y += car.c
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romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c
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romstage-y += gpio.c
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romstage-y += i2c_early.c
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romstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
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romstage-y += lpc_lib.c
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romstage-y += memmap.c
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@ -45,6 +46,7 @@ ramstage-y += cpu.c
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ramstage-y += chip.c
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ramstage-y += gpio.c
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ramstage-y += graphics.c
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ramstage-y += i2c.c
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ramstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
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ramstage-y += lpc.c
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ramstage-y += lpc_lib.c
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@ -69,6 +71,7 @@ postcar-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
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postcar-y += tsc_freq.c
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verstage-y += car.c
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verstage-y += i2c_early.c
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verstage-y += memmap.c
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verstage-y += mmap_boot.c
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verstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
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@ -18,7 +18,21 @@
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#ifndef _SOC_APOLLOLAKE_CHIP_H_
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#define _SOC_APOLLOLAKE_CHIP_H_
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#include <soc/gpio.h>
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#include <soc/intel/common/lpss_i2c.h>
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#include <device/i2c.h>
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#define CLKREQ_DISABLED 0xf
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#define APOLLOLAKE_I2C_DEV_MAX 8
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struct apollolake_i2c_config {
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/* Bus should be enabled prior to ramstage with temporary base */
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int early_init;
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/* Bus speed in Hz, default is I2C_SPEED_FAST (400 KHz) */
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enum i2c_speed speed;
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/* Specific bus speed configuration */
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struct lpss_i2c_speed_config speed_config[LPSS_I2C_SPEED_CONFIG_COUNT];
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};
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/* Serial IRQ control. SERIRQ_QUIET is the default (0). */
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enum serirq_mode {
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@ -79,6 +93,9 @@ struct soc_intel_apollolake_config {
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/* Integrated Sensor Hub */
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uint8_t integrated_sensor_hub_enable;
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/* I2C bus configuration */
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struct apollolake_i2c_config i2c[APOLLOLAKE_I2C_DEV_MAX];
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};
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#endif /* _SOC_APOLLOLAKE_CHIP_H_ */
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@ -0,0 +1,126 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2016 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/acpi_device.h>
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#include <arch/acpigen.h>
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#include <device/device.h>
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#include <device/i2c.h>
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#include <device/pci.h>
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#include <device/pci_def.h>
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#include <device/pci_ids.h>
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#include <soc/i2c.h>
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#include <soc/intel/common/lpss_i2c.h>
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#include <soc/pci_devs.h>
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#include <soc/pci_ids.h>
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#include "chip.h"
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uintptr_t lpss_i2c_base_address(unsigned bus)
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{
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unsigned devfn;
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struct device *dev;
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struct resource *res;
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/* bus -> devfn */
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devfn = i2c_bus_to_devfn(bus);
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if (devfn >= 0) {
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/* devfn -> dev */
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dev = dev_find_slot(0, devfn);
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if (dev) {
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/* dev -> bar0 */
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res = find_resource(dev, PCI_BASE_ADDRESS_0);
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if (res)
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return res->base;
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}
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}
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return (uintptr_t)NULL;
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}
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static int i2c_dev_to_bus(struct device *dev)
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{
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return i2c_devfn_to_bus(dev->path.pci.devfn);
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}
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/*
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* The device should already be enabled and out of reset,
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* either from early init in coreboot or FSP-S.
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*/
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static void i2c_dev_init(struct device *dev)
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{
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struct soc_intel_apollolake_config *config = dev->chip_info;
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const struct lpss_i2c_speed_config *sptr;
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enum i2c_speed speed;
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int i, bus = i2c_dev_to_bus(dev);
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if (!config || bus < 0)
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return;
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speed = config->i2c[bus].speed ? : I2C_SPEED_FAST;
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lpss_i2c_init(bus, speed);
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/* Apply custom speed config if it has been set by the board */
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for (i = 0; i < LPSS_I2C_SPEED_CONFIG_COUNT; i++) {
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sptr = &config->i2c[bus].speed_config[i];
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if (sptr->speed == speed) {
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lpss_i2c_set_speed_config(bus, sptr);
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break;
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}
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}
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}
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static void i2c_fill_ssdt(struct device *dev)
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{
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struct soc_intel_apollolake_config *config = dev->chip_info;
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int bus = i2c_dev_to_bus(dev);
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if (!config || bus < 0)
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return;
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acpigen_write_scope(acpi_device_path(dev));
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lpss_i2c_acpi_fill_ssdt(config->i2c[bus].speed_config);
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acpigen_pop_len();
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}
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static struct i2c_bus_operations i2c_bus_ops = {
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.dev_to_bus = &i2c_dev_to_bus,
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};
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static struct device_operations i2c_dev_ops = {
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.read_resources = &pci_dev_read_resources,
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.set_resources = &pci_dev_set_resources,
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.enable_resources = &pci_dev_enable_resources,
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.scan_bus = &scan_smbus,
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.ops_i2c_bus = &i2c_bus_ops,
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.init = &i2c_dev_init,
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.acpi_fill_ssdt_generator = &i2c_fill_ssdt,
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};
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static const unsigned short pci_device_ids[] = {
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PCI_DEVICE_ID_APOLLOLAKE_I2C0,
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PCI_DEVICE_ID_APOLLOLAKE_I2C1,
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PCI_DEVICE_ID_APOLLOLAKE_I2C2,
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PCI_DEVICE_ID_APOLLOLAKE_I2C3,
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PCI_DEVICE_ID_APOLLOLAKE_I2C4,
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PCI_DEVICE_ID_APOLLOLAKE_I2C5,
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PCI_DEVICE_ID_APOLLOLAKE_I2C6,
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PCI_DEVICE_ID_APOLLOLAKE_I2C7,
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0,
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};
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static const struct pci_driver pch_i2c __pci_driver = {
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.ops = &i2c_dev_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.devices = pci_device_ids,
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};
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@ -0,0 +1,116 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2016 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <commonlib/helpers.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/i2c.h>
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#include <device/pci_def.h>
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#include <soc/intel/common/lpss_i2c.h>
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#include <soc/i2c.h>
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#include <soc/iomap.h>
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#include <soc/pci_devs.h>
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#include "chip.h"
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static int i2c_early_init_bus(unsigned bus)
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{
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ROMSTAGE_CONST struct soc_intel_apollolake_config *config;
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ROMSTAGE_CONST struct device *tree_dev;
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const struct lpss_i2c_speed_config *sptr;
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enum i2c_speed speed;
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pci_devfn_t dev;
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unsigned devfn;
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uintptr_t base;
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uint32_t value;
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void *reg;
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/* Find the PCI device for this bus controller */
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devfn = i2c_bus_to_devfn(bus);
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if (devfn < 0) {
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printk(BIOS_ERR, "I2C%u device not found\n", bus);
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return -1;
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}
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/* Look up the controller device in the devicetree */
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dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn));
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tree_dev = dev_find_slot(0, devfn);
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if (!tree_dev || !tree_dev->enabled) {
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printk(BIOS_ERR, "I2C%u device not enabled\n", bus);
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return -1;
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}
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/* Skip if not enabled for early init */
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config = tree_dev->chip_info;
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if (!config || !config->i2c[bus].early_init) {
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printk(BIOS_ERR, "I2C%u not enabled for early init\n", bus);
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return -1;
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}
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/* Prepare early base address for access before memory */
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base = PRERAM_I2C_BASE_ADDRESS(bus);
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pci_write_config32(dev, PCI_BASE_ADDRESS_0, base);
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pci_write_config32(dev, PCI_COMMAND,
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PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
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/* Take device out of reset */
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reg = (void *)(base + I2C_LPSS_REG_RESET);
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value = read32(reg);
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value |= I2C_LPSS_RESET_RELEASE_HC;
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write32(reg, value);
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/* Initialize the controller */
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speed = config->i2c[bus].speed ? : I2C_SPEED_FAST;
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if (lpss_i2c_init(bus, speed) < 0) {
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printk(BIOS_ERR, "I2C%u failed to initialize\n", bus);
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return -1;
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}
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/* Apply custom speed config if it has been set by the board */
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for (value = 0; value < LPSS_I2C_SPEED_CONFIG_COUNT; value++) {
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sptr = &config->i2c[bus].speed_config[value];
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if (sptr->speed == speed) {
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lpss_i2c_set_speed_config(bus, sptr);
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break;
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}
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}
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return 0;
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}
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uintptr_t lpss_i2c_base_address(unsigned bus)
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{
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unsigned devfn;
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pci_devfn_t dev;
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uintptr_t base;
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/* Find device+function for this controller */
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devfn = i2c_bus_to_devfn(bus);
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if (devfn < 0)
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return (uintptr_t)NULL;
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/* Form a PCI address for this device */
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dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn));
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/* Read the first base address for this device */
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base = ALIGN_DOWN(pci_read_config32(dev, PCI_BASE_ADDRESS_0), 16);
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/* Attempt to initialize bus if base is not set yet */
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if (!base && !i2c_early_init_bus(bus))
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base = ALIGN_DOWN(pci_read_config32(dev, PCI_BASE_ADDRESS_0),
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16);
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return base;
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}
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@ -0,0 +1,50 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2016 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _SOC_APOLLOLAKE_I2C_H_
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#define _SOC_APOLLOLAKE_I2C_H_
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#include <device/pci_def.h>
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#include <soc/pci_devs.h>
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/* I2C Controller Reset in MMIO private region */
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#define I2C_LPSS_REG_RESET 0x204
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#define I2C_LPSS_RESET_RELEASE_HC ((1 << 1) | (1 << 0))
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#define I2C_LPSS_RESET_RELEASE_IDMA (1 << 2)
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/* Convert I2C bus number to PCI device and function */
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static inline int i2c_bus_to_devfn(unsigned bus)
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{
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if (bus >= 0 && bus <= 3)
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return PCI_DEVFN(LPSS_DEV_SLOT_I2C_D0, bus);
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else if (bus >= 4 && bus <= 7)
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return PCI_DEVFN(LPSS_DEV_SLOT_I2C_D1, (bus - 4));
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else
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return -1;
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}
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/* Convert PCI device and function to I2C bus number */
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static inline int i2c_devfn_to_bus(unsigned devfn)
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{
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if (PCI_SLOT(devfn) == LPSS_DEV_SLOT_I2C_D0)
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return PCI_FUNC(devfn);
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else if (PCI_SLOT(devfn) == LPSS_DEV_SLOT_I2C_D1)
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return PCI_FUNC(devfn) + 4;
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else
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return -1;
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}
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#endif /* _SOC_APOLLOLAKE_I2C_H_ */
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@ -31,6 +31,9 @@
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#define PMC_BAR1 0xfe044000
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/* Temporary BAR for SPI until PCI enumeration assigns a BAR in ramstage. */
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#define PRERAM_SPI_BASE_ADDRESS 0xfe010000
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#define PRERAM_SPI_BASE_ADDRESS 0xfe010000
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/* Temporary BAR for early I2C bus access */
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#define PRERAM_I2C_BASE_ADDRESS(x) (0xfe020000 + (0x1000 * (x)))
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#endif /* _SOC_APOLLOLAKE_IOMAP_H_ */
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