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soc/intel/apollolake: Enable write-protect SPI flash range support 

Use intel common infrastructure to enable support for write-protecting
SPI flash range. Also, enable this protection for RW_MRC_CACHE.

BUG=chrome-os-partner:58896
TEST=Verified that write to RW_MRC_CACHE fails in OS using
"flashrom -p host -i RW_MRC_CACHE -w /tmp/test.bin"

Change-Id: I35df12bc295d141e314ec2cb092d904842432394
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17117
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
This commit is contained in:
Furquan Shaikh 2016-10-24 15:28:23 -07:00 committed by Furquan Shaikh
parent 723a84e292
commit ffb3a2d225
3 changed files with 19 additions and 0 deletions
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2
src/soc/intel/apollolake/Kconfig
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@ -34,6 +34,7 @@ config CPU_SPECIFIC_OPTIONS
select HAVE_SMI_HANDLER select HAVE_SMI_HANDLER
select MMCONF_SUPPORT select MMCONF_SUPPORT
select MMCONF_SUPPORT_DEFAULT select MMCONF_SUPPORT_DEFAULT
select MRC_SETTINGS_PROTECT
select NO_FIXED_XIP_ROM_SIZE select NO_FIXED_XIP_ROM_SIZE
select NO_XIP_EARLY_STAGES select NO_XIP_EARLY_STAGES
select PARALLEL_MP select PARALLEL_MP
@ -52,6 +53,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
select SOC_INTEL_COMMON_LPSS_I2C select SOC_INTEL_COMMON_LPSS_I2C
select SOC_INTEL_COMMON_SMI select SOC_INTEL_COMMON_SMI
select SOC_INTEL_COMMON_SPI_PROTECT
select UDELAY_TSC select UDELAY_TSC
select TSC_CONSTANT_RATE select TSC_CONSTANT_RATE
select TSC_MONOTONIC_TIMER select TSC_MONOTONIC_TIMER

3
src/soc/intel/apollolake/include/soc/spi.h
View File

@ -33,9 +33,12 @@
#define SPIBAR_HSFSTS_CTL 0x04 #define SPIBAR_HSFSTS_CTL 0x04
#define SPIBAR_FADDR 0x08 #define SPIBAR_FADDR 0x08
#define SPIBAR_FDATA(n) (0x10 + ((n) & 0xf) * 4) #define SPIBAR_FDATA(n) (0x10 + ((n) & 0xf) * 4)
#define SPIBAR_FPR_BASE 0x84
#define SPIBAR_PTINX 0xcc #define SPIBAR_PTINX 0xcc
#define SPIBAR_PTDATA 0xd0 #define SPIBAR_PTDATA 0xd0
#define SPIBAR_FPR_MAX 5
/* Bit definitions and masks for BIOS_BFPREG register. */ /* Bit definitions and masks for BIOS_BFPREG register. */
#define SPIBAR_BFPREG_PRB_MASK (0x7fff) #define SPIBAR_BFPREG_PRB_MASK (0x7fff)
#define SPIBAR_BFPREG_PRL_SHIFT (16) #define SPIBAR_BFPREG_PRL_SHIFT (16)

14
src/soc/intel/apollolake/spi.c
View File

@ -21,6 +21,7 @@
#include <arch/io.h> #include <arch/io.h>
#include <device/device.h> #include <device/device.h>
#include <device/pci.h> #include <device/pci.h>
#include <soc/intel/common/spi.h>
#include <soc/pci_devs.h> #include <soc/pci_devs.h>
#include <soc/spi.h> #include <soc/spi.h>
#include <spi_flash.h> #include <spi_flash.h>
@ -393,3 +394,16 @@ int spi_read_status(uint8_t *status)
return 0; return 0;
} }
int spi_get_fpr_info(struct fpr_info *info)
{
BOILERPLATE_CREATE_CTX(ctx);
if (!ctx->mmio_base)
return -1;
info->base = ctx->mmio_base + SPIBAR_FPR_BASE;
info->max = SPIBAR_FPR_MAX;
return 0;
}