soc/intel/icelake: Select FSP_M_XIP
This patch ports CB:32275 changes from CNL to ICL. Ice Lake require that FSP-M component should be XIP. This change selects FSP_M_XIP so that the right arguments are passed into cbfstool when adding this component. Change-Id: Icc5550f1f94957fa1b28c8bba6fc0efee98e233e Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32507 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -19,6 +19,7 @@ config CPU_SPECIFIC_OPTIONS
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select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
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select COMMON_FADT
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select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
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select FSP_M_XIP
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select GENERIC_GPIO_LIB
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select HAVE_FSP_GOP
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select INTEL_DESCRIPTOR_MODE_CAPABLE
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