Commit Graph

4445 Commits

Author SHA1 Message Date
Felix Singer ad31061e66 util/liveiso: Update to NixOS 21.11
Update configs so that they work with NixOS 21.11. Drop `iasl` package
since it was replaced with `acpica-tools`.

Change-Id: Icb9a382b83b3b3e55126bb0bb508659d11497a05
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59881
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-12-06 22:37:08 +00:00
Patrick Georgi 987e3dc80b util/cbfstool: Ensure that htole32 et al are visible when building
endian.h wasn't included (although it probably came in as an indirect
include) but in some header sets _XOPEN_SOURCE overrides _DEFAULT_SOURCE
whereas the latter is a super set of the former:

We should get the same things as with _XOPEN_SOURCE (such as memccpy for
which it has been defined) but also extra features like htole32.

Change-Id: Iaee7495b2ae64fdc719ae0879ea95fe7df286212
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-12-06 19:40:53 +00:00
Jakub Czapiga ea619425ee commonlib: Move commonlib/cbmem_id.h to commonlib/bsd/
Libpayload requires cbmem_id.h file to support extracting values from
CBMEM IMD entries of coreboot tables. Libpayload use BSD-3-Clause
license, and all of its files used to compile a static library have to
use it too.

Change-Id: I97c080e34ebdbcdf14fe3a3c9515b1dea8ede179
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59696
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
2021-11-30 17:23:37 +00:00
Angel Pons 1186265898 util/cbfstool/.gitignore: Add CSE tool executables
Commit 796aeeba96 (util/cse_fpt: Add a new tool for managing Intel CSE
FPT binaries) and commit d7fb6a90e1 (util/cse_serger: Add a new tool
for stitching CSE components) add two utilities, and building cbfstool
also generates executables for them. When building cbfstool standalone,
these executables are placed in `util/cbfstool/`, and Git should never
track them.

Specify these executables' file names in .gitignore in order to prevent
unintentional inclusion of these files in commits, which is very likely
to happen when using `git add` on directories.

Change-Id: I285a4d7aeee642822eaae2eb69e5d52efb4bc8c0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59670
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-29 18:44:34 +00:00
Patrick Georgi 8422740933 util/ifdtool/Makefile: Derive from Makefile.inc
Instead of maintaining two complete Makefiles, reuse the coreboot
build system rules in the stand-alone Makefile.

Change-Id: I5d894a1f079799478bce0bd200ac735097f3806b
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59669
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-26 11:26:19 +00:00
Patrick Georgi 19072dcd6f util/testing: Add ifdtool to tools to be tested
Ensure that the separate Makefile doesn't break.

Change-Id: I0fbe37dc01e46022c5e6de5629eb99f6b86b0b14
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-11-26 10:20:37 +00:00
Angel Pons 1a55dbf7e9 util/ifdtool/Makefile: Fix building as standalone tool
Commit f1e401c6cb (util/cbfstool/flashmap/fmap.c: fix fmaptool
endianness bugs on BE) makes use of endianness conversion macros
in cbfstool's FMAP code, which is also used by ifdtool. At least
on Linux, the <endian.h> header provides these helpers, but only
when `__USE_MISC` is defined, which is defined in the <ctypes.h>
header when `_DEFAULT_SOURCE` is defined. This was accounted for
in `Makefile.inc`, but not in `Makefile`. As a result, trying to
build ifdtool as a standalone tool (i.e. not as part of building
a coreboot image) results in build errors because the endianness
conversion macros are not defined.

Define `_DEFAULT_SOURCE` in `Makefile` to fix the build errors.

Change-Id: I8c2bbc07ddd87d885e2d6f5c7f2bd501e5c4e3b0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59663
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-26 10:20:24 +00:00
Patrick Georgi 673716dedd util/testing: Give meaningful error if intel-sec-tools aren't around
Without manual handling, when 3rdparty/intel-sec-tools isn't around,
`make what-jenkins-does` reports only

    go: go.mod file not found in current directory or any parent directory; see 'go help modules'

which isn't meaningful or actionable. Instead check that the go.mod file
exists and bail out with a better error message before trying to run
`go mod vendor`.

Change-Id: I035747746ca5fd54841bd67352044dde12a28185
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-11-24 20:16:48 +00:00
Marek Kasiewicz f1e401c6cb util/cbfstool/flashmap/fmap.c: fix fmaptool endianness bugs on BE
This patch makes all accesses to the FMAP fields explicitly little endian.
It fixes issue where build on BE host produced different binary image than
on LE.

Signed-off-by: Marek Kasiewicz <marek.kasiewicz@3mdeb.com>
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Change-Id: Ia88c0625cefa1e594ac1849271a71c3aacc8ce78
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55039
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-11-22 15:01:30 +00:00
Hsuan Ting Chen a5cbe27148 eventlog: Add a log type for Chrome OS diagnostics
Add events for Chrome OS diagnostics in eventlog tool:
* ELOG_TYPE_CROS_DIAGNOSTICS(0xb6): diagnostics-related events
* ELOG_CROS_LAUNCH_DIAGNOSTICS(0x01): sub-type for diagnostics boot

These events are not added anywhere currently. They will be added in
another separate commit.

Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org>
Change-Id: I1b67fdb46f64db33f581cfb5635103c9f5bbb302
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-22 14:59:37 +00:00
Angel Pons ada539ee50 util/inteltool/gpio.c: Correct register name
Document 319973-003 (ICH10 datasheet) and document 324645-006 (6-series
PCH datasheet) indicate that the name of this register is `GP_LVL3`,
not `GPIO_LVL3`. Correct the name.

Change-Id: I44cc41843c9f7cd0796bd198fb89447d787f155a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2021-11-19 15:10:20 +00:00
Patrick Georgi 423e9e0fc0 Documentation/lint: Use Super I/O instead of SuperIO
Change-Id: Idb16092b687ebffb319bc1908f08f350d612d36a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39451
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-11-19 14:47:20 +00:00
Angel Pons 65adc70165 util/inteltool: Add ICH10D PCI ID
Add the PCI device ID for the ICH10D southbridge. While we're at it,
also fix up whitespace in inteltool.h of an adjacent definition.

Change-Id: I98d88a9ce27d3ddaafd7123ee51b2111a8bef019
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2021-11-19 13:54:48 +00:00
Sean Rhodes c9bc7a7591 util/lint: Fix linters to work with coreboot-configurator
* Exclude .gif files from newline checking
* Exclude coreboot-configurator from checkpatch checking

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I1b07b7b05340409e5c1695cc7bbdea68f8190097
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
2021-11-19 13:34:55 +00:00
Zheng Bao 570645dc2a amdfwtool: Call the set_efs_table for Stoneyridge
Related to https://review.coreboot.org/c/coreboot/+/58555
commit-id: 35b7e0a2d82ac
In 58555, we added the SOC ID for Stoneyridge in amdfwtool
command line. But it raised building error because it then called
"set_efs_table" without setting SPI mode. So we skipped calling that.

But in set_efs_table, it has case for Stoneyridge. The boards also
need to have this setting. So we remove the skipping and give the
proper SPI mode in mainboard Kconfig.

Change-Id: I24499ff6daf7878b12b6044496f53379116c598f
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-18 23:29:48 +00:00
Zheng Bao 6e2c5a3d18 amdfwtool: Set flag comboable as bool type
Fix the CL:
https://review.coreboot.org/c/coreboot/+/58942
The type comboable was int but set as true.

Change-Id: Id2c43378735c089a27a5aa683b55a0f7ec3677de
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-18 23:28:59 +00:00
Zheng Bao b749d3f0d2 amdfwtool: Add a union for combo and psp directory
For combo layout, this is for combo header.
For non-combo layout, this is for PSP directory.

Change-Id: Ie7b5aec6b511ad61972908d1d22a13aeb7dd73a9
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-18 23:28:47 +00:00
Reka Norman 86a9cdd589 util/mb/google: Change comments in memory Makefile.inc templates
Begin comments with # instead of ## to match the Makefile.inc generated
by spd_tools.

BUG=None
TEST=None

Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: If2d716a7338fd5af8216b2bcd894fc88a9df137e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-17 00:35:36 +00:00
Zheng Bao 6bc300d8d5 amdfwtool: Set soc name for Stoneyridge
For the stoneyridge, soc_name is not set in Makefile, so set_efs_table
is not called. Keep it unchanged.

Change-Id: I0e82188ce64733420a578446e22a077ef789be92
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-15 10:06:39 +00:00
Martin Roth 93e6bbad3c util/docker/coreboot-sdk: Add bsdextrautils & lcov
Add lcov for coverage calculations.
Add bsdextrautils for hexdump.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I421c59ce2d0d08bf5142dbc378eeea45b8b1d5b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59019
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
2021-11-14 04:21:10 +00:00
Zheng Bao 5164e4b03f amdfwtool: Pack out-of-bounds check into a function and move
Need to check the FWs number limit several times. So pack the
duplicated steps into a function. And do it before access the new
entry.

Change-Id: I71117d1c817c0b6ddaea4ea47aea91672cc6d55a
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-11 14:40:45 +00:00
Reka Norman e6a1ebe55b util/spd_tools: Document adding support for a new memory technology
Add documentation describing how to add support for a new memory
technology to spd_tools:
- Add a section to the README.
- Document the memTech interface in spd_gen.go.

BUG=b:191776301
TEST=None

Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: Ie710c1c686ddf5288db35cf43e5f1ac9b1974305
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59005
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-09 23:45:26 +00:00
Martin Roth a7648f2b27 util/lint/kconfig_lint: Fix off by one error that missed last line
This error prevented the last line of the Kconfig tree from being
printed or added to the output file.  This is a significant problem if
you try to use the generated file as the kconfig source, because it
changes CONFIG_HAVE_RAMSTAGE from defaulting to yes to defaulting to
NO.  This causes the build to stop working.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I3ec11f1ac59533a078fd3bd4d0dbee9df825a97a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58992
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-11-09 14:14:46 +00:00
Zheng Bao ba3af5e2ff amdfwtool: Change the flag value to type bool
Change-Id: I8bb87e6b16b323b26dd5b411e0063e2e9e333d05
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58942
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-05 12:56:19 +00:00
Zheng Bao edd1e360f4 amdfwtool: Fix the parameter point to NULL instead of integer
Change-Id: Iaeeec7a7e2de7847bfcefa5b7ff3f259f86533d4
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58941
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-05 12:55:35 +00:00
Zheng Bao 33351336f8 amdfwtool: Change the definition of level to a bitwise form
Change-Id: Icca393f0d69519cc1c3cb852a11dd7006cf72061
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-05 12:55:29 +00:00
Paul Fagerburg 5d4f0838d6 util/testing: add code coverage to jenkins
Add COV=1 and the `coverage-report` target to unit test build rules
in `what-jenkins-does` so that we get code coverage data from the
coreboot and libpayload unit tests.

Signed-off-by: Paul Fagerburg <pfagerburg@google.com>
Change-Id: I96669c47d1a48e9ab678a4b9cb1d0c8032d727f0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-11-04 20:34:53 +00:00
Reka Norman 2c439adb51 util/spd_tools: Add LP5 support for ADL
Add LP5 support to spd_tools. Currently, only Intel Alder Lake (ADL) is
supported.

The SPDs are generated based on a combination of:
- The LPDDR5 spec JESD209-5B.
- The SPD spec SPD4.1.2.M-2 (the LPDDR3/4 spec is used since JEDEC has
  not released an SPD spec for LPDDR5).
- Intel recommendations in advisory #616599.

BUG=b:201234943, b:198704251
TEST=Generate the SPD and manifests for a test part, and check that the
SPD matches Intel's expectation. More details in CB:58680.

Change-Id: Ic1e68d44f7c0ad64aa9904b7e1297d24bd5db56e
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58679
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-11-04 10:46:07 +00:00
Angel Pons 437da71d0a SMBIOS/SCONFIG: Allow devtree-defined Type 41 entries
Introduce the `smbios_dev_info` devicetree keyword to specify the
instance ID and RefDes (Reference Designation) of onboard devices.

Example syntax:

 device pci 1c.0 on	# PCIe Port #1
 	device pci 00.0 on
 		smbios_dev_info 6
 	end
 end
 device pci 1c.1 on	# PCIe Port #2
 	device pci 00.0 on
 		smbios_dev_info 42 "PCIe-PCI Time Machine"
 	end
 end

The `SMBIOS_TYPE41_PROVIDED_BY_DEVTREE` Kconfig option enables using
this syntax to control the generated Type 41 entries. When this option
is enabled, Type 41 entries are only autogenerated for devices with a
defined instance ID. This avoids having to keep track of which instance
IDs have been used for every device class.

Using `smbios_dev_info` when `SMBIOS_TYPE41_PROVIDED_BY_DEVTREE` is not
enabled will result in a build-time error, as the syntax is meaningless
in this case. This is done with preprocessor guards around the Type 41
members in `struct device` and the code which uses the guarded members.
Although the preprocessor usage isn't particularly elegant, adjusting
the devicetree syntax and/or grammar depending on a Kconfig option is
probably even worse.

Change-Id: Iecca9ada6ee1000674cb5dd7afd5c309d8e1a64b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-11-04 10:25:09 +00:00
Patrick Georgi 6dad77d64a util/crossgcc/Makefile: Clean up .PHONY definitions
Order functionally:
 * first "all" and build-$tools
 * followed by clean
 * followed by the architecture targets

The order was chosen this way because the architecture targets are
the mostly likely to continue to grow.

While at it, also fix the build_nasm mention (it was build-nasm)
and add build_make.

Change-Id: Id58338a512d44111b41503d4c14c08be50d51cde
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58796
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-02 17:36:23 +00:00
Patrick Georgi dba7736104 util/kconfig: Uprev to Linux 5.15's kconfig
Upstream's changes only affect a script that we don't use.
Still, this keeps us in sync with the official version.

Change-Id: I39cbbfb8dc816b4f36f92e6bd53f40c733691242
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-11-02 08:10:47 +00:00
Patrick Georgi 9f7c78b5ec util/kconfig: Uprev to Linux 5.14's kconfig
Upstream's changes have been minimal, to the perl script that we
don't use and a constness change, so I expect no harm. Still, this
keeps us in sync with the official version.

Change-Id: I5e5a2400bc3323938da4b946930e2ec119819672
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-11-02 08:10:41 +00:00
Patrick Georgi c710ee7319 util/kconfig: Rewrite patch in quilt's normal form
This is what quilt writes on `quilt refresh` and what it can apply and
unapply cleanly.

Change-Id: I8c8586da384b65fd5c21c1c1a093642534f83283
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57878
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-11-02 06:40:41 +00:00
Patrick Georgi f32eed1695 buildgcc: Remove GDB from crossgcc
It was added for a specific defunct project by a specific defunct
company.

Change-Id: Ib56ae0fdc1a50d24ff44c7879c43f8e94a5bfa95
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2021-11-01 16:26:50 +00:00
Zheng Bao eb0404e8bf amdfwtool: Add PSP ID for combo and ISH header for A/B recovery
Nobody calls the function until combo or A/B is added, so suppress the
warning for now.

Test=Majolica (Cezanne)

Change-Id: I3082b850fb3fd2d7ae83a1c4dfd89eb7e1bd0f97
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55551
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-10-29 14:26:22 +00:00
Ricardo Quesada e1f392ea34 elogtool: add pytest for elogtool
This CL adds a python test for elogtool.
It tests the basic functionality of elogtool: list, clear and add.
A future CL will include more complex tests.

BUG=b:172210863
TEST=pytest elogtool_test.py

Change-Id: If1241ad070d1c690c84f5ca61c0487ba27c2a287
Signed-off-by: Ricardo Quesada <ricardoq@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-10-25 08:08:41 +00:00
Timofey Komarov 6c8008283c util/inteltool: Add PCH IDs for 200 series chipsets
Signed-off-by: Timofey Komarov <happycorsair@yandex.ru>
Change-Id: Iadad5e79aef9da3fac627adc135525a5001a72b6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-24 16:04:49 +00:00
Felix Singer ff6416f737 util/release/build-release: Create cross-toolchain version file
Add cross-toolchain version file to the release tarball, which can be
used for pre-setting the variables used in buildgcc.

Change-Id: Iad1e0adaa95b71f161caf978276bfb0a63eac8f4
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58399
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-21 14:15:57 +00:00
Felix Singer 02750d0400 util/crossgcc/buildgcc: Use pre-set CROSSGCC_VERSION if possible
For reproducibility, a version string is appended to the version of the
tools used in the cross-toolchain. Currently, git is used to determine
that version string at runtime of this script. There are cases, where
it's not possible to determine that version string, e.g. when a release
tarball is used, and if so, the version string is just `v_`.

Thus, allow pre-setting the variable `CROSSGCC_VERSION`.

Change-Id: I888ccd877c93436b5e033528c43bd8667b8d2f10
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58396
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-21 14:15:29 +00:00
Felix Singer 60c56be85f util/crossgcc/buildgcc: Allow printing only the version
In preperation to CB:58396, add the parameter `-W|--print-version`,
which allows printing the content of `CROSSGCC_VERSION`. In
combination with CB:58396, this can be used to pre-set the variable
in case of the git history is not accessible.

Change-Id: I9a205ca0ecb0ece47eb5d8fa73706478354512ff
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-20 20:12:43 +00:00
Felix Singer 62fcffb247 util/crossgcc/buildgcc: Remove CROSSGCC_COMMIT
For reproducibility, the buildgcc script is copied to the destination
folder of the toolchain. `CROSSGCC_COMMIT` is used as a file name
extension for the script and was introduced when `CROSSGCC_VERSION`
didn't contain the commit yet. Since this is not the case anymore,
remove it.

Change-Id: Id0a0b657eb828b2728ff787228eaa38be83d9517
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58450
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-20 20:12:19 +00:00
Raul E Rangel 41ba01bb95 util/cbfstool/rmodule: Omit undefined extern symbols from reloc table
When using `DECLARE_OPTIONAL_REGION`, it is assumed that
REGION_SIZE(name) == 0 if the region was not defined in the memlayout.
When using non-rmodule stages (i.e., bootblock, romstage, etc), this
assumption holds true, but breaks down in rmodule (i.e., ramstage)
stages.

The rmodule tool is not currently omitting undefined externals from the
relocation table. e.g.,

    extern u8 _##name##_size[];

This means that when the rmodule loader runs, it will rewrite the symbol
from 0 (which is the default the linker assumed) to 0 + offset. This is
wrong since the symbol doesn't actually exist. Instead we need to omit
the relocation so it continues to keep the default value of 0.

BUG=b:179699789
TEST=Print out REGION_SIZE(cbfs_cache) in ramstage and verify it is set
to 0.
I also see the following printed by the rmodtool now:

DEBUG: Omitting relocation for undefined extern: _watchdog_tombstone_size
DEBUG: Omitting relocation for undefined extern: _watchdog_tombstone
DEBUG: Omitting relocation for undefined extern: _watchdog_tombstone
DEBUG: Omitting relocation for absolute symbol: _stack_size
DEBUG: Omitting relocation for absolute symbol: _program_size
DEBUG: Omitting relocation for absolute symbol: _cbmem_init_hooks_size
DEBUG: Omitting relocation for absolute symbol: _payload_preload_cache_size
DEBUG: Omitting relocation for absolute symbol: _payload_preload_cache
DEBUG: Omitting relocation for absolute symbol: _payload_preload_cache_size
DEBUG: Omitting relocation for absolute symbol: _payload_preload_cache
DEBUG: Omitting relocation for undefined extern: _cbfs_cache
DEBUG: Omitting relocation for undefined extern: _cbfs_cache_size

As you can see the _watchdog_tombstone will also be fixed by this CL.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ib57e263fa9014da4f6854637000c1c8ad8eb351a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-20 15:56:28 +00:00
Michael Niewöhner 4396358fd3 kconfig_lint: use just one variable for keeping track of choices
Instead of using two variables, one for the boolean value and one for
the path, use just one with the path. Since an empty string evalutes to
false, this simplification does not change behaviour.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I2f1171789af6815094446f107f3c634332a3427e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-10-20 15:52:16 +00:00
Michael Niewöhner 70fb5cb514 kconfig_lint: put $inside_choice together right in the first place
Instead of substituting the delimiter later, put $inside_choice together
right in the first place.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: Ia713510a683101c48c86a1c3722ebb1607a29288
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-10-20 15:51:36 +00:00
Furquan Shaikh bf848ad4b2 util/cse_serger: Add command `create-cse-region`
This change adds a new command `create-cse-region` to cse_serger tool
which takes as inputs offset:size and file for different CSE
partitions and generates the entire CSE region image.

BUG=b:189177186

Change-Id: Ib087f5516e5beb6390831ef4e34b0b067d3fbc8b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58215
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-19 16:32:24 +00:00
Furquan Shaikh 8b4ca15d7e util/cse_serger: Replace cse_layout_regions with array of regions
This change replaces `struct cse_layout_regions` with an array of
`struct region` and introduces enums for DP and BP[1-4]. This makes it
easier to loop over the different regions in following changes.

BUG=b:189177186

Change-Id: If3cced4506d26dc534047cb9c385aaa9418d8522
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-19 16:10:12 +00:00
Furquan Shaikh 555f040772 util/cse*: Add cse_helpers.{c,h}
This change moves `read_member` and `write_member` helper functions
out of cse_fpt.c and cse_serger.c into cse_helpers.c to avoid
duplication.

BUG=b:189177186,b:189167923

Change-Id: I7b646b29c9058d892bb0fc9824ef1b4340d2510c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-19 16:08:45 +00:00
Furquan Shaikh d7fb6a90e1 util/cse_serger: Add a new tool for stitching CSE components
This change adds a new tool `cse_serger` which can be used to print,
dump and stitch together different components for the CSE region.

BUG=b:189177186

Change-Id: I90dd809b47fd16afdc80e66431312721082496aa
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55503
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-19 16:08:24 +00:00
Furquan Shaikh 796aeeba96 util/cse_fpt: Add a new tool for managing Intel CSE FPT binaries
This change adds a new tool `cse_fpt` which can be used to print and
dump CSE partitions in Flash Partition Table (FPT) format.

BUG=b:189167923

Change-Id: I93c8d33e9baa327cbdab918a14f2f7a039953be6
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55259
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-19 16:08:03 +00:00
Felix Held ad68b07d45 util/amdfwtool: rename PSP related embedded_firmware struct elements
The element at offset 0x14 in the embedded_firmware struct is the
pointer to the combo PSP directory header, so rename it from comboable
to combo_psp_directory to clarify that this is not a flag, but a pointer
to a data structure. Also rename psp_entry to psp_directory since it
points to the PSP directory table.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic6149c17ae813f4dcea71c308054849a1a2e4394
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58419
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-10-19 12:35:08 +00:00
Furquan Shaikh 2bfef8d856 cbfstool: Add helper function `buffer_from_file_aligned_size`
This change adds a helper function `buffer_from_file_aligned_size`
that loads a file into memory buffer by creating a memory buffer of
size rounded up to the provided `size_granularity` parameter.

BUG=b:189177186,b:189167923

Change-Id: Iad3430d476abcdad850505ac50e36cd5d5deecb4
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-18 21:15:41 +00:00
Nico Huber 967730f565 kconfig_lint: Drop overly restrictive rule about choice configs
This rule was creating trouble:
* A symbol may only be declared inside or outside a choice.

The linter treats every occurence of a `config` entry as a symbol
declaration, even when it's just setting a default or adding selects.
This is not easy to fix as the symbol objects are not created first
and then added to the $symbols array when we know what kind of decla-
ration we have, but are created incrementally inside this global
list.

Change-Id: I48a17f6403470251be6b6d44bb82a8bdcbefe9f6
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56410
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-18 19:33:57 +00:00
Jakub Czapiga 12ae850dfc libpayload: Add unit-tests framework and first test case
This commit adds a unit-tests framework ported from coreboot, and test
for drivers/speaker. Usage of the unit-tests framework is same as for
the coreboot one.

Change-Id: Iaa94ee4dcdc3f74af830113813df0e8fb0b31e4f
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-10-18 12:33:49 +00:00
Angel Pons 05ae8f2ff3 mainboard: Drop invalid `VGA_BIOS_FILE` defaults
If the VGA BIOS file path for `VGA_BIOS_FILE` in a mainboard's Kconfig
does not exist in the coreboot tree (including submodules), drop it.
These files should be stored in the `site-local` subdirectory and the
paths specified for each board in `site-local/Kconfig`. For example:

config VGA_BIOS_FILE
	default "site-local/x200_vbios.bin" if BOARD_LENOVO_X200

Note that this is just an example. There are better ways to structure
one's `site-local` subfolder. Using the `CONFIG_MAINBOARD_DIR` option
would be one of them, though variants may still need special handling.

Also, update autoport to not generate `VGA_BIOS_FILE` defaults.

Change-Id: I1b5dfba035a42d7943f270f95fb7d32b285584d2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2021-10-15 09:08:35 +00:00
Nicholas Chin 87e0b5b1d7 util/autoport/bd82x6x.go: Fix includes
Fix include of nvs.h to reflect commit 661ad4666c (ACPI: Select
ACPI_SOC_NVS only where suitable); and re-add <device/pci_ops.h>,
removed in commit 0aad0531dc (util/autoport/bd82x6x.go: Drop unused
includes), as the generated early_init.c uses pci_write_config16().

Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Change-Id: Ic1e97cfa7dce0e4d25f7a37c28d3635bdbf6c2a5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-10-12 17:37:52 +00:00
Rex-BC Chen 5020fe3449 util/cbfstool: Add support for ARM64 UefiPayload
UEFI payload is supported on some ARM64 platforms, for example MT8195.
As a result, add MACHINE_TYPE_ARM64 to support ARM SystemReady.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I4c0c6e263bd2f518a62ff9db44d72dd31086756a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-10-04 02:31:01 +00:00
Felix Singer ae90f2ebc5 util/liveiso: Install nvme-cli tool
nvme-cli is used to manage NVMe devices and it supports many vendors.
Also, it seems it's commonly used to do firmware updates.

Change-Id: I26a78867b01d3af0441827c5b25343a46d7ddea1
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-10-01 15:08:07 +00:00
Reka Norman 91feb06ece Revert "Revert "util/abuild: Regenerate xcompile on every abuild run""
This reverts commit d94f8bbe9d.

This is a reland of https://review.coreboot.org/57651. The original
change broke parallel abuild runs since the xcompile file was deleted by
every recursive call to abuild. This issue was fixed by rebasing on top
of a change which only regenerates the xcompile on non-recursive calls.

BUG=None
TEST=Parallel abuild run succeeds.

Change-Id: I086ba7b2ae1b8b14459838bd18ce962a84aa306d
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57913
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-09-26 16:08:05 +00:00
Ricardo Quesada 1427f12adf elogtool: Fix off-by-one error in month in timestamp
elogtool was setting the timestamp with the wrong value in the month.
This CL fixes that by incrementing the month by one. This is needed
since gmtime() returns the month value starting at 0.

TEST=pytest elogtool_test.py (see next CL in relation chain)

Change-Id: I00f89ed99b049caafba2e47feae3c068245f9021
Signed-off-by: Ricardo Quesada <ricardoq@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-09-24 18:08:43 +00:00
Nico Huber e28eeb713d util/abuild: Run `make .xcompile` only once
If abuild called itself recursively, the file already exists and we can
spare us one evaluation of all the makefiles per recursive abuild run.

Change-Id: Id3e2239354ec251c24c03c971987586deeb026c5
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-09-24 14:32:07 +00:00
Michael Niewöhner 90fcffb416 kconfig_lint: restrict definition of defaults for choice elements
Defining defaults for symbols used inside choices is not allowed. Add a
check for this, so we can drop the existent, overly restrictive checks
in the follow-up change.

Change-Id: I45bce2633dbd168fceb81ceae9b68621b28526e8
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57715
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-09-23 22:25:53 +00:00
Patrick Georgi b0d87f753c util/crossgcc: Update gcc to 11.2
Various fixes to gnat and the improved nds32 backend have been merged
into gcc by now, so we don't need to carry those patches anymore.

Change-Id: Icdee2a8beedd109ee1f0eef6f32f7accbf66674b
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54050
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-09-23 08:37:39 +00:00
Reka Norman e4cf38ed36 util/spd_tools: Remove old lp4x and ddr4 versions of spd_tools
The migration to the new unified version of spd_tools is complete, so
the old lp4x and ddr4 versions can be removed.

BUG=b:191776301
TEST=None

Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: I6b1fc297739efc8dc7d7eec64956bf3343984604
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-23 07:51:38 +00:00
Reka Norman 8f690dd762 util/spd_tools: Sort platforms_manifest entries by set number
Ensure that the order of entries in each platform manifest is consistent
every time spd_gen is run.

BUG=b:191776301
TEST=Run spd_gen for lp4x and ddr4, check that the manifests are
unchanged.

Change-Id: I7bfea65c8fc781df80a8725c0cf20c7547c857e8
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-23 07:51:22 +00:00
Reka Norman 0c1f737fea util/mb/google: Update templates to refer to the new spd_tools
Update the new variant templates to refer to the new unified version
of spd_tools:
- Update the comments in mem_parts_used.txt
- Change the placeholder SPD in Makefile.inc to 'placeholder'

BUG=b:191776301
TEST=None

Change-Id: I03265de0d1182da81dd25a2fe6f940a0b82e5fa4
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-23 06:52:27 +00:00
Zheng Bao b1fb8cebf8 amdfwtool: Add an optional column of level
The value of level defined in table is the default one. We now give an
extra option in config file to change this value so some FWs can be
dropped in a more optimized way.
For the non A/B recovery mode, The value could be L1, L2, Lb or Lx,
which are level 1, leve 2, level both and using default value. If it
is empty or Lx, left the level in table unchanged.

Give a redundant field [12bxBX] in regular exprssion for A/B recovery
which will be done later.

Change-Id: I0847bc3793467a2299f14d1d2d2486f3f858d7f3
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57612
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-23 06:26:47 +00:00
Reka Norman 293a3e03dc util/spd_tools: Remove PLK platform
Currently spd_tools treats PCO and PLK as separate platforms. This is
unnecessary since they have the same SPD requirements. Remove PLK, and
use PCO as the platform for all zork variants.

BUG=b:191776301
TEST=None

Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: I7eeeab53fb3e0d92c3675fb80b4747297d4257ab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-23 06:23:46 +00:00
Reka Norman 7adc2e23b5 util/spd_tools: Add README for unified spd_tools
Combine the existing lp4x and ddr4 READMEs into a single file, and
update it to reflect the new unified version of the tools.

BUG=b:191776301
TEST=None

Change-Id: I866932a1d0b5b6b47b0daff893b37de7a302b4e6
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57796
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-23 06:21:31 +00:00
Reka Norman f4be6f6d85 util/spd_tools: Add 'Generated by' string to part_id_gen output files
Add a 'Generated by' string to the generated Makefile.inc and
dram_id.generated.txt, showing the command used to generate the files.

BUG=b:191776301
TEST=Run part_id_gen, check that the generated files contain the string

Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: Ic9a7826212a732288f36f111b7bc20365a1f702d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57692
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-21 17:21:49 +00:00
Reka Norman 4e4e2d7ab1 util/spd_tools: Automatically determine the SPD dir in part_id_gen
Currently, one of the arguments to part_id_gen is the directory
containing the SPD files, e.g. spd/lp4x/set-0. This requires the user of
the tool to understand the spd/ directory structure, and manually look
up the set number corresponding to their platform.

Change part_id_gen to take the platform and memory technology as
arguments instead of the SPD directory, and automatically determine the
SPD directory by reading the platforms manifest file generated by
spd_gen.go.

BUG=b:191776301
TEST=Run part_id_gen and check that the generated Makefile.inc and
dram_id.generated.txt are the same as before. Example:
util/spd_tools/bin/part_id_gen \
  ADL \
  lp4x \
  src/mainboard/google/brya/variants/kano/memory \
  src/mainboard/google/brya/variants/kano/memory/mem_parts_used.txt

Change-Id: I7cd7243d76b5769e8a15daa56b8438274bdd8e96
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-21 17:21:39 +00:00
Reka Norman 780b04e639 util/spd_tools: Add max ID check for auto-generated IDs to part_id_gen
Currently, the maximum part ID of 15 is enforced only for manually
assigned IDs. Also enforce it for automatically assigned IDs.

BUG=b:191776301
TEST=part_id_gen fails when the number of part IDs which would be
assigned is greater than MaxMemoryId.

Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: I802190a13b68439ccbcdb28300ccc5fd1b38a9c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57691
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-21 17:21:23 +00:00
Frank Wu f894fcc031 util: Add DDR4 generic SPD for 4JQA-0622AD
Add SPD support for DDR4 memory part

BUG=b:199469240
TEST=none

Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: Ie67cf6b90304f0bcf80838866c7461c0cea86dc3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57550
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-21 15:19:10 +00:00
Reka Norman d94f8bbe9d Revert "util/abuild: Regenerate xcompile on every abuild run"
This reverts commit a2c009bd94.

Reason for revert: Breaks parallel abuilds.

Change-Id: I368b189050d519769f4852fea8e255e9b31b27b6
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57590
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-21 10:56:37 +00:00
Ricardo Quesada e48043b095 elogtool: compile in 32-bit platforms
This CL fixes a compilation error that happens in 32-bit platforms.
This error happens because printf() was using %ld instead of %zu to
print size_t variables.

This CL fixes it.

BUG=b:200608182
TEST=emerge-kevin (ARM 32-bit)
TEST=emerge-eve (Intel 64-bit)

Change-Id: I340e108361c052601f2b126db45caf2e35ee7ace
Signed-off-by: Ricardo Quesada <ricardoq@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-09-21 01:02:56 +00:00
Reka Norman b05edb1fea util/spd_tools: Implement a unified version of the part_id_gen tool
Currently there are two versions of gen_part_id.go, one for LP4x and one
DDR4. This change implements a unified version of this tool.

The new part_id_gen.go is almost identical to the existing
ddr4/gen_part_id.go. The new version was based on the ddr4 version and
not the lp4x version, since the ddr4 version contains extra logic to
support fixed IDs in the mem_parts_used files.

The only non-trivial change from ddr4/gen_part_id.go is to include the
full paths of SPD files in the generated Makefile.inc. E.g. instead of

  SPD_SOURCES += lp4x-spd-1.hex

the full path relative to the coreboot root directory is included:

  SPD_SOURCES += spd/lp4x/set-0/spd-1.hex

BUG=b:191776301
TEST=For each variant of brya/volteer/dedede/guybrush/zork, run
part_id_gen and verify that the generated Makefile.inc and
dram_id.generated.txt are identical to those currently in the src tree,
except for the modified SPD file paths in Makefile.inc.
Example:
util/spd_tools/bin/part_id_gen \
  spd/lp4x/set-0 \
  src/mainboard/google/brya/variants/kano/memory \
  src/mainboard/google/brya/variants/kano/memory/mem_parts_used.txt

Change-Id: Ib33d09076f340f688519dae7956a2b27af090c0b
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-20 23:51:07 +00:00
Reka Norman a2c009bd94 util/abuild: Regenerate xcompile on every abuild run
Currently, running abuild in a fresh checkout without having built the
toolchain results in the following confusing behaviour:
1. Run abuild. It fails due to the missing coreboot toolchain, and the
   error message suggests running `make crossgcc`.
2. Run `make crossgcc`. It succeeds.
3. Re-run abuild. It still fails due to a missing coreboot toolchain.

This happens because the first abuild run generates an xcompile file
which uses the system toolchain. The second abuild run doesn't
regenerate the xcompile, so it still fails due to the non-coreboot
toolchain.

To avoid this confusing behaviour, regenerate the xcompile file every
time abuild is run.

BUG=None
TEST=Perform the steps above in a clean checkout. The second abuild run
now succeeds.

Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: I78a7702c45cecbfe8460ec55df03741e5ced94b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-09-20 12:21:05 +00:00
Furquan Shaikh 0df32c85ad sconfig: Emit device structure pointers if alias names are provided
This change uses _dev_${ALIAS_NAME} as the name for `struct device` if
the device has an alias. In addition to that, it emits
_dev_${ALIAS_NAME}_ptr which points to the device structure. This
allows developers to directly reference a particular device in the tree
using alias name without having to walk the entire path. In later CLs,
mainboards are transitioned to use this newly emitted device structure
pointers.

Change-Id: I8306d9efba8e5ca5c0bda41baac9c90ad8b73ece
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-20 12:17:13 +00:00
Patrick Georgi f28e368d58 util/crossgcc: Update binutils to 2.37
Change-Id: Ia68d4d9f836ad23fb8f6a7203a78b4ea40c7c43b
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-09-19 18:51:52 +00:00
Reka Norman 0e79274d33 util/spd_tools: Implement a unified version of the spd_gen tool
Currently there are two versions of spd_tools: one for LP4x and one for
DDR4. This change is the first step in unifying these into a single
tool.

This change implements a unified version of the spd_gen tool, by
combining the functionality currently in lp4x/gen_spd.go and
ddr4/gen_spd.go. The unified version takes the memory technology as an
argument, and generates SPD files for all platforms supporting that
technology.

BUG=b:191776301
TEST=Compare the SPDs generated by the old and new versions of the tool
for all supported platforms. For reference, the test script used is
here: https://review.coreboot.org/c/coreboot/+/57511

Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: I7fc036996dbafbb54e075da0c3ac2ea0886a6db2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57512
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-09-17 14:49:22 +00:00
Zheng Bao 2079589999 amdfwtool: Detect the flag multilevel to decide the actual value
To save the space for FW, some of the FWs are going to be defined as
LVL2 entries. To be compatible to "flattened" layout, we still drop
the LVL2 entry to level1 if there is only one level.

Change-Id: Ibe8cdd5c14225899352b02bb19aae6059d56d428
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57063
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-09-17 14:48:30 +00:00
Felix Singer 7a474a5bb7 util/liveiso: Make neovim the default editor
Make neovim the default editor and create an alias for vim.

The NixOS module for neovim is currently broken. Thus, add a note to
`description.md` to switch to that later.

Change-Id: I9345a6e32f3035565e55e50579c97121b4987d83
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57393
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-16 22:55:50 +00:00
Felix Singer 821311e23e util/nixshell: Add Nix shell for toolchain compilation
Add a Nix shell file which provides an environment for compilation of
the coreboot toolchain. The Nix shell can be used by running the
following command:

  $ nix-shell --pure util/nixshell/toolchain.nix

The `--pure` parameter is optional, but it makes sure that the
environment is as minimal as possible and does not contain any unrelated
or unneeded software or configuration.

Once compiled, the coreboot toolchain can be used without loading the
shell environment.

If `--pure` is used, SSL connections won't work since the
`SSL_CERT_FILE` environment variable is not configured, which makes the
build tool unable to download the source files. Thus, let it point to
the system certificate store.

Change-Id: I341ee28c5451d2c6cb4ff22de67161d99f4ca77a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57646
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-09-16 22:55:02 +00:00
Ricardo Quesada 683b294d3f elogtool: add "add" command
Adds "add" command to elogtool. This command allows adding elog events
manually. It supports event type and, optionally, event data.

If the free buffer space is < 1/4 of the total space, it shrinks the
buffer, making sure that ~1/4 of the free space is available.

BUG=b:172210863
TEST=./elogtool add 0x17 0101
     ./elogtool add 0x18
     Repeated the same tests on buffers that needed to be shrunk.

Change-Id: Ia6fdf4f951565f842d1bff52173811b52f617f66
Signed-off-by: Ricardo Quesada <ricardoq@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-16 17:28:16 +00:00
Ricardo Quesada a2bf94d4c1 elogtool: add next_available_event_offset function
This function is "extracted" from cmd_clear().
This new function will be called from cmd_add(), and new command that
will be added in a future CL (see CL chain).

Additional minor fixes:
 - calls usage() if no valid commands are passed.
 - Slightly improves usage() output. Needed for cmd_clear()

BUG=b:172210863
TEST=elogtool clear

Change-Id: I0d8ecc893675758d7f90845282a588d367b55567
Signed-off-by: Ricardo Quesada <ricardoq@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-16 13:52:37 +00:00
Tim Wawrzynczak 5cd979efb5 util/sconfig: Update static.c to include boot/coreboot_tables.h
This allows the devicetree to directly access names defined in the
coreboot tables API.

BUG=b:194967458
BRANCH=dedede

Change-Id: Ieb2d00095f54b2363a21f9c5ef8205110a36f746
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-16 00:12:28 +00:00
Zheng Bao 535ec536ea amdfwtool: Add new SOC mendocino
Change-Id: I54492600dd954a5585ce3b1d842d264a4a50907a
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56936
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-09-15 16:50:44 +00:00
Felix Singer 5e44322532 util/liveiso: Install UEFITool packages
Install both versions of UEFITool, the one with the old engine and the
new one.

It's not possible to use both packages in the same environment, since
there is a collision between the names of the binary files. To make sure
a specific package is used, a new environment needs to be spawned with
the following command:

  $ nix-shell -p <package_name>

The UEFITool binaries can be executed from the shell then.

Change-Id: Ia5d679c6e7cd01c2ab819bd6c085596a926c494d
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-09-15 11:42:59 +00:00
Patrick Georgi 615cdfcdb9 util/kconfig: Add pre-built parser
It avoids the dependency on bison/flex, minimally speeds up the build
and also works around weird race conditions in some versions of bison
that need more investigation.

The issue this avoids manifests as a build error when creating
parser.tab.c:

    input in flex scanner failed
    make: *** [util/kconfig/Makefile.inc:66: build/util/kconfig/parser.tab.c] Error 2

Since the error happens within bison the alternative would be to make
bison part of our crossgcc environment to ensure that no broken OS
build is used.

BUG=b:197515860
TEST=things build with bison not installed

Change-Id: Ib35dfb7beafc0a09dc333e962b1e3f33df46a854
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-13 15:35:03 +00:00
Patrick Georgi 116b144930 util/kconfig: Simplify dependencies for parser.tab.*
With parser.tab.h depending on parser.tab.c it's possible for make
to initiate the creation of parser.tab.c, then try to compile it,
even though parser.tab.h is still missing.

This isn't normally an issue yet because bison creates them both at
a time but with pre-compiled files this will become a problem.

Pattern rules support (until recently as a special case that no other
type of rule could implement) multiple targets that are actually
treated as "one command creates multiple output files" so use that
to state the relationship properly.

Change-Id: I4aa7eca9d3123808e0665a15a99c04fac7384940
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57509
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-13 14:49:15 +00:00
Angel Pons d56d2a86ed util/sconfig: Extract handling of SMBIOS data
Move the code that handles devices' SMBIOS data into a helper function.

Change-Id: I4f36d6c6f26e79558d360d319d09b0b8426def0e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57369
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-13 13:58:20 +00:00
Angel Pons 39e029768b util/sconfig: Always generate SMBIOS CPP guards
Manually maintaining a list of fields just to avoid printing some
unnecessary CPP guards isn't worth the maintenance burden. Instead,
always generate these guards, even if they guard nothing.

Change-Id: I6c84180d83ac39a895e02d196acb7074eb052d7f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57459
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-13 13:55:59 +00:00
Ricardo Quesada 49a96a9463 elogtool: add "clear" command
Adds "clear" command to cbfsutil/elogtool tool.
"clear" clears the RW_ELOG region by using either:
 * flashrom if no file is provided
 * or using file write if an input file is provided.

The region is filled with ELOG_TYPE_EOL. And a
ELOG_TYPE_LOG_CLEAR event is inserted.

Additionally, it does a minor cleanup to command "list", like:
 * use buffer_end()
 * add "list" to the cmds struct
 * and make elog_read() very similar to elog_write()

Usage:
$ elogtool clear

BUG=b:172210863
TEST=elogtool clear && elogtool list
     elogtool clear -f invalid.raw
     elogtool clear -f valid.raw

Change-Id: Ia28a6eb34c82103ab078a0841b022e2e5e430585
Signed-off-by: Ricardo Quesada <ricardoq@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
2021-09-10 22:53:05 +00:00
Felix Singer 593941b600 util/liveiso/console.nix: Remove unneeded argument body
Change-Id: Iebd994a46e870e42431d0fc71dd14b1c2b01f9aa
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57536
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-10 20:09:08 +00:00
Felix Singer 46e109f274 util/liveiso: Disable strict checking of access to MMIO memory
Change-Id: Ie859490d3cb3b8c56437cbd6c3e46525c580d3f4
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57535
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-10 20:09:02 +00:00
Julius Werner 8202fc42d4 util/cbmem: Add -2/--2ndtolast option to print second-to-last boot log
On some platforms, runtime firmware crashes write logs to the CBMEM
console. For those, since a crash reboots the system, by the time we
have a chance to run `cbmem` again the boot where the crash happened
will be the one before the "last" (current) boot. So cbmem -1 doesn't
show the interesting part, and cbmem -c potentially shows a lot that is
cumbersome to dig through. This patch introduces a new option cbmem -2
to explicitly show only the boot cycle before the last one.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I6725698f4c9ae07011cbacf0928544cebb4ad6f8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
2021-09-09 23:05:03 +00:00
Martin Roth a95cd265bd util/amdtools: Add script to update the SPI speed in the EFS header
The update_efs_spi_speed allows changing the SPI speed manually in a
binary that has already been built.  This will allow binaries not built
for the EM100 SPI ROM emulator to be updated so that they will work.
There is a corresponding change that will check to see if the EFS value
has been modified from the original speed and will prevent coreboot from
updating the SPI speed and mode.

BUG=b:177233017
TEST=Update SPI speed in existing binary.  See that SPI speed has
changed.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I905a9fd8bd93a28aab927dffecbbcf24934b9e03
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56644
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-08 19:41:31 +00:00
Nico Huber 859ecdf517 sconfig: Ensure at least one `device` node below each `chip`
Even though `device` entries are children of `chip` entries in the
devicetree source format, the chips in the translated C structures
are only hooked up to device nodes. Hence, any chip with all its
settings will be silently dropped by sconfig if there is no device
node below it.

Let's adapt the parser to ensure that there is at least one `device`
entry. The intermediate `chipchildren_dev` rule applies until the
first `device` entry is found, then everything continues as before
with the `chipchildren` rule.

Change-Id: I54830bc1fc7d00a0605f3fe4d36a83ef57ef3312
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51119
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-08 19:03:20 +00:00
Iru Cai 112e9baddf autoport: search for the HDA device on PCH
Haswell has its Mini-HD device and is at card0, so we need to search
for the PCH HD Audio device instead of using card0.

Change-Id: I2bc420fdbe9731ae835f63add85db79f04201da4
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34357
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-06 19:35:26 +00:00
Iru Cai ab5cac2c79 inteltool: Support dumping IOBP register values
This patch also adds LynxPoint and WildcatPoint-LP IOBP registers,
which is used to get the USB and SATA configuration values for
autoport.

Change-Id: I1f11640fdff59a5317f19057476f7e48c2956ab9
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41473
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-06 19:35:08 +00:00
Felix Held a6274992ff utils/abuild: select FSP_USE_REPO instead of ADD_FSP_BINARIES
Like USE_AMD_BLOBS and USE_QC_BLOBS in the case of the AMD and Qualcomm
repos, FSP_USE_REPO controls if the Intel FSP repo will get checked out
and will be available during the Jenkins runs. ADD_FSP_BINARIES will get
selected in drivers/intel/fsp2_0/Kconfig when FSP_USE_REPO is selected.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I72faa6f9e5f2b06ab7cd43595ae0b49bf4d39630
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-09-05 17:52:38 +00:00