Rembrandt has different data fabric component IDs compared to Mendocino.
PPR #56558 Rev 3.04 was used as a reference.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3c840a3e071a289d9e02143ee790c26faeda029d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Split the signed AMDFW binaries into their own section and enable PSP
verstage.
BUG=b:284984667
TEST=Build Myst BIOS image with PSP Verstage. Boot to OS successfully
with PSP verstage and a separate section for signed AMDFW binaries.
Change-Id: Ie0a54c157ebdebf9a0c95933c96865e0782a0f90
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75703
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
With reference to the Picasso PPR 55570 Rev 3.18, LegacyIoEn bit is 0 on
reset and setting it will enable the decoding of the following legacy IO
ports:
0x20, 0x21, 0xA0, 0xA1 (PIC);
0x40, 0x41, 0x42, 0x43, 0x61 (8254 timer);
0x70, 0x71, 0x72, 0x73 (RTC);
0x92.
Verstage does not use those legacy IO ports. Also newer SoCs like
Phoenix do not support Legacy I/O registers to access Power Management
registers and accessing them from PSP verstage causes a hang. Hence
enable legacy IO only on platforms that support it.
BUG=b::284984667
TEST=Build Myst BIOS image with PSP Verstage. Boot to OS successfully
with PSP verstage.
Change-Id: I5e74b4cd1fa7e942770976e5e2197ded47503660
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76692
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I20fe63e93121b3b791e6d475e948b6ada648293b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77073
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Neither cap, hcdn_reg, disable_relaxed_ordering nor ht_link_up are used,
so drop the fields from struct bus.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I655b028107da7ddcb5caa03dab55b022387e7cb9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77072
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Add the required files to support VBOOT for when it is enabled.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I842b79d8e144414ce42b3d0d9dfd2b5180ecf70d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74230
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Adjust the Type-C output ports to "Integrated Displayport" to comply
with FSP 4221.
Change-Id: Ifcb4a086106f90c70926f44a7566330efd185544
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Disable PSR in the VBT to avoid flickering on kernels later than 5.15.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I3640fcea73e278e6c8968a4b0c9ba7cf04a2361f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77134
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Disable PSR in the VBT to avoid flickering on kernels later than 5.15.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I5b58f4d26fa0032a5aed3af0db71a5daf41fdd8c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76941
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable "CnviBtCore" and "CnviBtAudioOffload" to increase
bluetooth performance.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ibafabfaa39ba46620a2e06b288c457267f041ab0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
If the version of the EC firmware in coreboot doesn't match
the firmware that the EC is running, print the versions.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I55c09b8d5ffe8ca9135384c823d005b55cfd83d9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76380
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Switch the TGL variant to use the "merlin" EC variant, and delete the
no longer needed "TGL" EC variant.
This is not a functional change.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Id4d305490b48c1c79ea52b0bbaa79b675412e0b4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76332
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Switch the ADL variant to use the "merlin" EC variant, and delete the
no longer needed "ADL" EC variant.
This is not a functional change.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I61e56cc95a26be60d7f10c89d26bce2d857ae81a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76313
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The UCSI mailbox isn't used, so remove it.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I03587a2322b1f34fa26a5c2ba7906a4e1ae82ae0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76254
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Merlin was the name for the open-source variant of the EC. It
ended up getting entirely rewritten to work with SDCC, and is
currently being used on starbook/adl. The source code isn't
available at the time of this commit due to some old ITE XLT
code being used.
Add the latest version of the code, replacing the old code, so
the boards can be migrated over.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ib8384fc9322058297e8219ac8e483ac37a70bd33
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Recent ChromeOS devices use Ti50 instead of Cr50. Therefore, some
strings or comments are not accurate anymore. When applicable, rename
Cr50 to GSC (Google security chip).
BUG=b:275544927
TEST=./util/abuild/abuild -x -t GOOGLE_TOMATO -a
BRANCH=none
Cq-Depend: chromium:4756700
Change-Id: Ie5b9267191a5588830ed99a8382ba1a01933028f
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Updating from commit id 034907b2:
2023-06-03 08:10:11 +0000 - (vboot_reference: eliminate redundant call to write protect EC-RO)
to commit id 0c11187c:
2023-08-07 11:41:45 +0000 - (vboot_reference: Rename Cr50 to GSC when applicable)
This brings in 38 new commits:
0c11187c vboot_reference: Rename Cr50 to GSC when applicable
76c160e2 futility: updater: Support --unlock_me with --mode=output
48a12071 futility: Add `show` test for CBFS integration firmware
b419912f futility: Pull file names into ft_show_bios() subtypes
db56d9c5 futility: Clarify `name` and remove `data` argument of file type funcs
311f59e8 futility: Use -P for signing tests
854c71b9 tests: futility: Make test_show_contents easier to update
5f5a695e futility: Document machine parseable format guidelines
774c700f futility: Fix HWID digest footer output
8cc8b710 futility: Fix build with a single RW partition and CBFS verification
6d4b03e5 futility/cmd_read.c: Implement --split-path|-s switch
636d5b16 Correct a malloc() check in VbExStreamOpen()
def2f5af firmware/2lib: Switch to RO immediately if only one slot present
9c9931b4 futility/cmd_read.c: Optimise to limit SPI transaction
cb56129f checkpatch: Change max line length from 80 to 96
aa23241a tests: Fix run_vbutil_kernel_arg_tests.sh
d7c26f52 futility: Follow-up fixes to CL:4548417
56490778 futility: add machine friendly print option
23e750b8 tests: Remove duplicate test for vb2api_fail()
612d140b futility: updater: fix custom label devices using customization_id
69cbe7ee Revert "futility: Avoid unnecessary servo control command"
290b72d6 vbutil_kernel: Drop alignment check for EFI stub
5d582eb5 sign_android_image.sh: Preserve capabilities for EROFS as well
8c30aaab futility: Avoid unnecessary servo control command
58f8bb5c futility: Fix flash teardown issue
2d9f9cdb sign_official_build: add cloud-signing param
d0ceeee6 image_signing: sign_official_build: create a proper main() func
38cfb9b0 Revert "make_dev_ssd.sh: Add support for kdump"
2c43e4dd .clang-format: Change the ColumnLimit from 80 to 96
3107ce77 host/lib/flashrom_drv.c: Check chip len symmetrically across R/W ops
0549e3c1 2load_kernel: Change bootloader_address out-parameter to offset
979f61de Make sign_android_image.sh support EROFS image format as well.
bb5ccd7d lib/flashrom_drv.c: Pass regions as pointer + size.
249a3477 vbutil_kernel: Move kernel's EFI boot stub into bootloader section
c8998d5f host/lib: Use absolute path for flashrom
564d9274 futility/updater_utils.c: Drop flashrom cli producer
9bf3edf8 futility/updater.c: Clarify conditions of do_update
212643bd futility/updater.c: Use canonical defines
Change-Id: I0947f0f6670328b779d2a8ef240ca196ef615cec
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
The command "git branch -a | grep -q ${branch}" may not exit with 0 when
pipefail is set. "grep -q" exits immediately with exit code 0 as soon as
a match is found. However, at that point "git branch -a" may be still
writing to the pipe, leading to SIGPIPE. When pipefail is set,
PIPESTATUS 141 will be returned. Fix the problem by not using "grep -q".
Also fix the branch name in the generated commit subject.
Change-Id: Ic07efb5e2a4f3b7bbc6e76da9e026771bc685bdb
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77085
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Width of registers are always dwords on pl011, not bytes.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I955319d31bba5c0cd4d50f2b34111d51fea653ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
The use of a separate _PRW is not necessary when the _CRS interrupt
already has the Wake flag set (as these all do). Additionally, Windows
does not allow the use of a gpioint for the _PRW source, which results
in an ACPI_BIOS_ERROR BSOD.
Since ChromeOS builds for CYAN devices use an older kernel and may not
make use of _CRS interrupt Wake flag, keep the _PRW around when
CONFIG_CHROMEOS is selected.
TEST=build/boot Win11 on google/{cyan,edgar}
Change-Id: I7d0883e4de9572a14c8bad0ac086370bd00eeb1a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76798
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Specify the size of the ME region so that it matches the IFD.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I51ba0a7646ab72d4dd22b99519708649c78b25b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
This patch creates a new variant karis4es.
The new variant will support only ESx samples. The existing karis
variant will support the QS samples.
BUG=b:293326312
TEST=Image built properly
Change-Id: I854fee7206528a235f027ff8ec98593a02be4806
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76761
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Add configs for USB 3.1 Gen2 electrical validation (EV) settings
so that people can set the EV settings per board in device tree.
BUG=b:285811345
TEST=build coreboot and fsp with enabled fw_debug.
Flashed to taranza and checked the log.
All usb configs were set correctly.
Change-Id: Iecd12d3db76b63ad99887dee5991d94d47f138fd
Signed-off-by: Chia-Ling Hou <chia-ling.hou@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76246
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This is unused - other references were removed long ago.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ia7a65f54c736db20a5440795fdfaa8be31ef971f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
´config´ is removed from measure list (CB:74750)
Add 'config' to ram_stage_additional_list[] to have it measured and
verified.
BUG=NA
TEST=boot and verify coreboot logs on facebook FBG1701
Change-Id: Id4119bc3a01e11f14a091facf81964d1a71092c1
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
The change does the following:
- adds PCH IDs for 700 series chipsets per the DOC# 619362 rev 2.2
- updates GPIO table for PCH-S per the DOC# 618659 rev 2.1
- enables dumping GPIOs for 700 series PCH
Change-Id: I4509ad714772ce90cdee5135227c02640acb6085
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75873
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
IT8784E is basically a IT8786E stripped from serial ports 3-6.
There are very few minor register differences in EC IO space and GPIO
LDN, which are covered by this patch.
Based on IT8784E-I Preliminary Specification V0.7.1 (non-public).
TEST=Dump SIO configuration on Protectli VP4670 (vault_cml).
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I5de8aeaff9697b854281391083f77a1083d12fe6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
This reduce the difference with linux v6.5-rc4.
Change-Id: I64bbc09b531ea217514601386dd517af92aa40f1
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70200
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reduce the difference with linux v6.5-rc4. and check for
const static or static <non ptr type> const declarations.
Change-Id: Ib4b37e130f2edbfe0385f0707a8c910a244bcfc7
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70202
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
This reduces the difference with linux v6.5-rc4.
Change-Id: I9f0e9f12a177c32b401fda74cbb30c5c259b3744
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
This reduces the difference with linux v6.5-rc4.
Change-Id: I59d9619f2e58f24e0a5474bcfa79351e3afb933d
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
This reduce the difference with linux v6.5-rc4.
Change-Id: I63b3561471d3bd0ebfe7e5733c6dd6fb673904e0
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65829
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
PPRs #57254 Rev 1.52 and #57255 Rev 0.33 were used as a reference.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie54fd6c5a82f368018d0b5fb811a6c9220c2c70b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77079
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
PPRs #57019 Rev 3.05 and #57396 Rev 3.06 were used as a reference.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id0fe478a710ecc1f2c8b36347aaf2d1634ebba9a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77078
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
PPRs #57243 Rev 3.02 and #56558 Rev 3.04 were used as a reference.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ibabe8faa79e3dcd02f4c885d29b9634645947b98
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77077
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
PPR #56569 Rev 3.04 was used as a reference.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Idfac7d996c6de9ea7c6adf2760de0ad97ffb9ec0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77076
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
PPR #55570 Rev 3.18 was used as a reference.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ide492f4479b85cd885044bbf74d8bf18c12e552b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77075
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
device/device.h provides struct device.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie03f6d15d94f2858e293b9f57505034263c03bbe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77074
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Prior to commit d1c0f958d1 ("acpi: Call acpi_fill_ssdt() only for
enabled devices"), uart_inject_ssdt() was used to set the ACPI status
(_STA) for both enabled and disabled devices. The aforementioned commit
limited it to being called only on enabled devices, which left disabled
devices without any _STA method at all -- which the OS assumes means
that the device is present and enabled.
To fix this, create the _STA method in the UART asl code for each port,
and set the return value to a name variable (STAT) which defaults to
0 (not present/disabled). Then, have uart_inject_ssdt() set STAT to
present and enabled (0xF) for UARTs actually present on the board.
TEST=build/boot google/skyrim (frostflow), dump ACPI tables, and verify
that _STA returns 0xF only for UARTs enabled in devicetree.
Change-Id: Id89e74c3ea7f53280935898ee35311b7cf3b152a
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77092
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Kahlee selects AMD_SOC_CONSOLE_UART causing UART0 to be used as console,
so enable uart_0 in the devicetree to make sure that the UART will be
marked as enabled in the SSDT that will be generated with the next patch
applied. This also matches the other AMD SoC based Chromebooks.
Change-Id: Ibe18f87d8bf63603fb2eb87728395e45e9a9ef69
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77094
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Define the UARTs as MMIO devices in the chipset devicetrees. Drop ACPI
_STA in asl since now handled by common SSDT generator. Implement
wait_for_aoac_enabled() since required by SoC common code, and ensure
compiled during all stages necessary.
TEST=build/boot google/liara, verify console UART still functional.
Change-Id: Ibecafdfa189d9c63a29b63759c5b965d03719009
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77093
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit 5dfec71829.
Reason for revert: This change made it impossible to disable ASPM by
FSP parameter. ASPM_DISABLE would result in the FSP parameter not
being programmed, causing it to be the FSP default value instead.
This additionally fixes MTL to match ADL.
Change-Id: I60c0ea08513fcb0035449ea3fef1681de528c545
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75280
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change-Id: I56ee0d4a26931fe05d2d35046325901930086e35
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76344
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
TESTED=On Intel AC, after seleting DISPLAY_UPD_IIO_DATA to compare
IIO UPD data are expected. lspci -vvv result is also normal.
Change-Id: Icfc2a22cb2e1f95be6bfc1d712e620e19a23ce27
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76343
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Felix Held