Turn on LPC decoding in romstage.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit 5d9dae5a1fdab1bf6c418dc7e6de28069bd342dc)
Change-Id: I937eb5c5b6c6a9f7a13ebd0bec7fcc8d789427ce
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17227
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Add ALC286 commands and update the PLATFORM_CONFIGURATION structure
with the list address.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit 2dd5cd2f01cd37c9eb7dff85e20e446c7d5ab2ee)
Change-Id: I037b39a8634bf886f82ed93488f1efbf6661c93f
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17226
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Change the Carrizo settings used for Bettong to ones specific
to Stoney on Gardenia.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit e99b2c7e2c913413fdc83ad37c5519837a38c7fb)
Change-Id: I4376421c8c08dab9d7ff1428993eed3978e89657
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17225
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Duplicate the code from DB-FT3lc and use the correct names.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit 935cbe6e8b81f11291322dba3688b0a5a0c3291c)
Change-Id: I3a3c62f09819ea02388bf70945fd0c011ad7555a
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17224
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Remove a duplicated check and setting for xHCI during the
AMD_INIT_RESET callout. This is handled by the wrapper. Also
remove nearby commented code. EcChannel0 is not a member of
FCH_RESET_DATA_BLOCK.
Leave the check in AMD_INIT_ENV. Although AGESA honors what
was previously requested, additional settings depend on the
state of Usb.Xhci0Enable.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit ca862fbacbe80b1345ad6f23262a9769f05c50fd)
Change-Id: I45a5123e158cd7399d6d286999371d4a0e0fa963
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17223
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Change the default configuration for the following settings:
AGPIO14: BT radio disable
AGPIO64: NFC PU
AGPIO65: NFC wake
AGPIO66: Webcam
AGPIO69: PCIe presence detect
AGPIO70: GPS sleep
AGPIO116: MUX for Power Express Eval
EGPIO119: SD power
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit d146af183b9dbbd6bd6c7b6ad1b383bf36203da4)
Change-Id: Ibbde7593f3477e30a45fd4f56f236c6e94e3725f
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17222
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Remove the last bit of Bettong board_id checking from Gardenia.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit b617823d1d2860a3f6d766a40ae95e5486739a5c)
Change-Id: Ibc56dbbfa1b15b21ebadb9f6c9c54936566a2986
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17221
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Gardenia doesn't have the ability to modify settings depending on
the board ID.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit 536b4c424e5259ddbd82469f5f426d3189ff3f89)
Change-Id: I2c928431306c669735cf735042855e95721bb107
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17220
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Gardenia makes no special considerations for a board_id regarding
SPD access and addressing. Remove this from the source and use
the standard AGESA call.
Make SPD address changes to devicetree.cb. Note that Gardenia is
designed to be a two channel, single DIMM/channel system (some SKUs
with two DIMMs on the second channel). However, this port is for
the Stoney processor which is a single channel. As a result, the
second DIMM slot is not usable. A future improvement could involve
a port using a different processor, with unique devicetree files
for each.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit 77511f98f819dfe08c3ed16ebc11e1b328bdca15)
Change-Id: Id00c2be83340ceeec043ec86e96779e6bf46ae7b
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17219
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Use bettong as the reference for the gardenia mainboard.
Update makefiles etc so it builds.
This patch intentionlly keeps the carrizo_fch.asl file to
remain synchronized with the AMD PI package.
Remove items that do not apply to the Stoney APU, rewrite the
comments associated with the PCIe devices, and fix up the
SPD register association to match the 00670F00 chip.h.
Original-Signed-off-by: Marc Jones <marcj303@gmail.com>
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
(cherry picked from commit 82accfcf9ec76a042156fb6e528f7900987b6e7e)
Change-Id: I014fec5c99c01fc02e129be514b704c8ba27d464
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17218
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Enable default acpi path PCI0.LPCB if TPM support is
selected in the kconfig system and the acpi path is not set via
acpi_name callback in the platform code.
Thanks to Aaron Durbin for providing this fix.
Change-Id: Idb56cafe71efc8a52eee5a5a663478da99152360
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/17855
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The earlier loop exits gracefully iff i == index. In other cases, member
might be NULL, so check that the scan was successful before using its
results.
Change-Id: I818c233d797d82fa819243c4626dd9c4b7de3ac6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1129147
Reviewed-on: https://review.coreboot.org/17887
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Add custom files for Sandybridge and IvyBridge functions.
Move only the minimal required functions into separate files.
Both files' functions are going to call raminit_common functions.
No functionality is changed.
Sandybridge code path tested on Lenovo T420.
Change-Id: I1b1dfbd0857b59d3ae4392b73c033ee7a5aed243
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/17605
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Some part of preram cbmem console output is truncated.
Increase preram cbmem console size to 0xd00 to avoid the same.
Change-Id: Idbcbb3d1f433668a0e5375679f56fbe562d39ddd
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/17840
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Sometime preram cbmem logs are truncated due to lack of
space (default preram cbmem console size is 0xc00).
Provide Kconfig option to configure preram cbmem console
size so that mainboard can configure it to required value.
Change-Id: I221d9170c547d41d8bd678a3a8b3bca6a76ccd2e
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/17839
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
On Netburst (Pentium 4) the fsb cannot be read from
MSR_FSB_FREQ (msr 0xcd). One has to use msr 0x2c instead.
Change-Id: I0beccba2e4a8ec5cd23537b2207f9c49a040fd73
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17832
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Add power management type config option that allows mainboards to
either:
1. Define a power resource that uses the reset and enable gpios to
power on and off the device using _ON and _OFF methods, or
2. Export reset and enable GPIOs in _CRS and _DSD so that the OS can
directly toggle the GPIOs as required.
GPIO type needs to be updated in drivers_i2c_generic_config to use
acpi_gpio type so that it can be used for both the above cases.
BUG=chrome-os-partner:60194
BRANCH=None
TEST=Verified that elan touchscreen works fine on reef using exported
GPIOs.
Change-Id: I4d76f193f615cfc4520869dedc55505c109042f6
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17797
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Enable the actual touch devices to be probed by the kernel
and remove the placeholder devices that I put in before
and were used for initial bringup.
BUG=chrome-os-partner:58666
TEST=tested on eve
Change-Id: I7fc6f9da83b1abbae6dd069f759b220d59153d1c
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/17896
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
When trying to bring up a device with a malfunctioning TPM2 chip, the
driver currently gets stuck waiting for SPI flow control, causing
bricked devices.
This patch puts a 100 ms cap on the waiting time - this should be
enough even for a longest NVRAM save operation which could be under
way on the TPM device.
BRANCH=gru
BUG=chrome-os-partner:59807
TEST=with a matching change in depthcharge, now a gru with corrupted
SPI TPM comes up to the recovery screen (it was not showing signs
of life before this change).
Change-Id: I63ef5dde8dddd9afeae91e396c157a1a37d47c80
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/17898
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
It was unsigned, not a good place to be for testing < 0.
Change-Id: I126fe86422900bbae2c3ca16052be27985cfed53
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1241911
Reviewed-on: https://review.coreboot.org/17888
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)
It's later tested for NULL, but never initialized to make that test work
reliably.
Change-Id: Iadee1af224507a6dd39956306f3eafa687895176
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1323515
Reviewed-on: https://review.coreboot.org/17880
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
filebuffer is treated like a string, so it should be zero-terminated
like a string.
Change-Id: I078aa39906394be64023424731fe0c7ae2019899
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1323473
Reviewed-on: https://review.coreboot.org/17878
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Change-Id: Ic1d1b85a1d7e85b555a93b3a0b55fe310b26e34a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1353362
Reviewed-on: https://review.coreboot.org/17875
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Put the UART pins into native mode in bootblock so they are not
floating when we try to communicate with H1 over I2C. Without
a serial console enabled BIOS these pins were not configured
until ramstage.
BUG=chrome-os-partner:60935
TEST=Boot Eve board without serial console and H1 TPM enabled
Change-Id: I30f3bf0bacc1bbd776b351a9c09748b0601c39bc
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/17893
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Add a generic I2C-HID driver for these types of devices that
do not need extra functionality. This allows a new device to
be added without having to write a new driver.
The i2c-hid PNP0C50 is automatically added as the _CID for the
device in the ACPI Device.
BUG=chrome-os-partner:58666
TEST=used on eve to describe a new i2c-hid touch controller
Change-Id: I94e9531a72f9bf1d6b3ade362b88883b21b83d0a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/17856
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
The Roda Lizard RV11 is a comparatively lightweight, full-rugged
notebook. It's based on a 17W TDP dual core Ivy Bridge CPU.
The Lizard RW11 is its bigger brother (45W TDP quad core, more i/o
options).
The RV11 is the first board to use the native graphics initialization
by libgfxinit. Tested so far, are the internal eDP port, DP and VGA.
Change-Id: Iea283059ce3402dc36184baf16928b55285a9eeb
Signed-off-by: Dennis Wassenberg <dennis.wassenberg@secunet.com>
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17446
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Changes:
o Verification that the framebuffer matches the display mode
o Automatic upscaling if the framebuffer resolution is lower
than the display mode's
o VGA-plane support
o HDMI pixel rate is limited to hardware constraints
o Error tolerant handling of EDID header-pattern
Change-Id: Icbfdf5f37caf99f66847a71f784730aced0826ab
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17775
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
To make the generated descriptor compatible with latest libflashrom.
Change-Id: I005159dd24e72da9cc43119103c96c5dd5b90a55
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17447
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Checking for memory self refresh can generate false positives,
as explained in faa6beb: "northbridge/intel/i945:
CHECK_SLFRCS_ON_RESUME Kconfig option".
This seems to be the case for this motherboard.
TESTED on ga-945gcm-s2l.
Change-Id: Iadf0a73b054470b652e1dc02557fb1715131f823
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17617
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
The type3 SMBIOS table has a non-optional SKU field at the end,
which causes a parsing error when missing. Add but do not populate it.
Change-Id: I988d0626b8680740697e1db58eb6d0b87874bfde
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/17851
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
ToString() requires the input buffer data to be null-terminated,
but the data returned by the EC is not, leading Windows to fail
to report any battery data at all. Correct this by concatenating
a null terminator (0x00) to the end of the buffer data before
inputting to ToString() where needed
Change-Id: Ic86048d1d6354b9b0dac3c8957df318d0825c905
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/17783
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
For Chrome OS the normal MRC cache should be cleared when a hardware
retrain recovery request is observed. The reason is that since there
are 2 different MRC cache slots there needs to be a mechanism which
allows an end user make a system bootable again if the MRC settings
happen to not allow the system to boot any longer. Therefore, one
just needs to enter recovery with the hardware retrain flag and
the system normal MRC cache slot will be invalidated.
BUG=chrome-os-partner:60592
BRANCH=reef
Change-Id: I6ad32ed0dd217d66404b77467a88689a06044544
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17871
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Allow a board/platform to invalidate the normal MRC cache when
hardware retraining is requested in recovery mode. A small 4 byte
payload is used to update the latest data written. It will of course
fail on MRC cache retreival on next usage.
BUG=chrome-os-partner:60592
BRANCH=reef
Change-Id: Ic88cd66802664813562d003f50d54e4a4ea375ef
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17870
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The EC switches, including the hardware retrain flag, are
cleared when handing off the vboot state in romstage. However,
one may still want to query the state of the hardware retrain
flag. Thus, add a method to get the flag from cbmem.
BUG=chrome-os-partner:60592
BRANCH=reef
Change-Id: Ic76cfb3255a8d3c179d5f8b13fa13c518f79faa2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17869
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
The cbmem_possibly_online() is a helpful construct. Therefore,
push it into cbmem.h so other users can take advantage of it.
BUG=chrome-os-partner:60592
BRANCH=reef
Change-Id: If5a1c7815ed03874dcf141014b8ffefb82b7cc92
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17868
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Rely on boot_device_spi_flash() to provide the spi_flash
object. There's no need to duplicate the probing logic.
BUG=chrome-os-partner:56151
BRANCH=reef
Change-Id: I91900a3dfad7ba92cbd3b0ace77b08db04cff0b6
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17867
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
We might not care much about this buffer, but we really use it later
on...
Change-Id: Ia16270f836d05d8b454e77de7b5babeb6bb05d6d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1294797
Reviewed-on: https://review.coreboot.org/17860
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)
VARIANT_DIR is defined in coreboot/Makefile.inc, so doesn't need to be
defined in each mainboard.
Change-Id: Ic93957b710e4a9863774de7fcf3bd006696b6aa1
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17841
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Marshall Dawson