Commit Graph

44871 Commits

Author SHA1 Message Date
Julian Stecklina 15235b2d89 emulation/qemu-i440fx,q35: avoid writing to ROM
libcbfs has a workaround to avoid writing to ROM areas:

        /* Hacky way to not load programs over read only media. The stages
         * that would hit this path initialize themselves. */
        if ((ENV_BOOTBLOCK || ENV_SEPARATE_VERSTAGE) &&
            !CONFIG(NO_XIP_EARLY_STAGES) && CONFIG(BOOT_DEVICE_MEMORY_MAPPED)) {

This workaround is not triggered in QEMU, because
BOOT_DEVICE_MEMORY_MAPPED is only selected for SPI boot devices. This
results in confusing (to the VMM developer) writes to read-only
memory.

As far as I can tell, this issue is weird but harmless, because the
code does memcpy to ROM with source == destination. The concensus in
the mailing list thread [1] was that it's worthwhile to be fixed
regardless.

[1] https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/message/KDI6YQCPXSQF4NDUAAC7TIXQKSZ6T4X7/

Change-Id: I5cefbc31f917021236105f7dc969118d612ac399
Signed-off-by: Julian Stecklina <julian.stecklina@cyberus-technology.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-11-23 09:20:28 +00:00
Sheng-Liang Pan f1dbd67381 mb/google/trogdor: change pin define for quackingstick
change TP_EN pin to GPIO_67 for quackingstick

BUG=b:206862167
BRANCH=trogdor
TEST=make

Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: I7cc1083111f46cd3489cbbb9e579c34dc972b0b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Bob Moragues <moragues@google.com>
2021-11-23 09:20:05 +00:00
Ben Chuang e987845fef drivers/genesyslogic/gl9750: Add driver for Genesys Logic GL9750
The device is a PCIe Gen1 to SD 3.0 card reader controller to be
used in the Chromebook. The datasheet name is GL9750S and the revision
is 01.

The patch disables ASPM L0s.

BUG=b:206014046
TEST=Verify GL9750 enters L1 by observing CLKREQ# de-asserts.

Signed-off-by: Ben Chuang <benchuanggli@gmail.com>
Change-Id: I6d60cef41baade7457a159d3ce2f8d2e6b66e71c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-23 09:19:25 +00:00
Martin Roth ea6a93f140 Makefiles: Hide skipping submodule info unless V=1
Currently, git prints out the submodules that are being skipped twice
on many builds.  This patch hides that output unless the build is set
to show it with `make V=1`.  This is the normal way of showing the extra
information during the build.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I7b5c7f1f79dcc88793a9a21f2e92e7accc5de1e0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59511
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-22 19:00:08 +00:00
Raul E Rangel 1d565b500d cpu/intel/hyperthreading: Add missing header <arch/cpu.h>
This file is using cpuid_result and cpuid(). I also removed the spinlock
header since it's not used. This is what was previously providing the
cpu.h header.

BUG=b:179699789
TEST=none

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Idc3daa64562c4a4d57b678f13726509b480ba050
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59356
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-11-22 16:59:45 +00:00
Rob Barnes 5e3c454fbb drivers/tpm: Add firmware-power-managed DSD property
Introduce firmware-power-managed DSD ACPI property for TPM devices.
This property can be checked by the kernel TPM driver to override how
the TPM power states are managed. This is a tri-state flag, true,
false, or unset. So an enum used to keep the flag is unset by default.

When firmware-power-managed is true, the kernel driver will not send a
shutdown during s2idle/s0i3 suspend.

BUG=b:200578885
BRANCH=None
TEST=TPM shutdown is triggered on s0ix suspend on guybrush with patched
kernel

Change-Id: Ia48ead856fc0c6e637a2e07a5ecc58423f599c5b
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-22 16:31:34 +00:00
Rob Barnes b35acf9210 soc/amd/psp_verstage: Init TPM on S0i3 resume
Add option to initialize the TPM in PSP verstage during s0i3 resume.
This is needed if the TPM is reset in s0i3. FSDL is handling
restoring everything else, so only the minimum TPM initialization is done.
Move aoac and i2c init before psp_verstrage_s0i3_resume becasue i2c
needs to be ready before attempting to restore tpm.

BUG=b:200578885,b:197965075
TEST=Multiple cycles of S0i3 suspend resume. ~66ms of additional delay.
BRANCH=None

Change-Id: Ie511928da6a8b4be62621fd2c4c31a8d1e724d48
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-11-22 16:30:08 +00:00
Patrick Georgi 2c89d08d7e Documentation: Add warning about "private" changes on Gerrit
Private changes on Gerrit are a tricky beast in that they're well hidden
in the UI and a few other places but still reachable under certain
circumstances.

Change-Id: I1c8c6cccfd023bc1d839dc5d9544204c88f89c7e
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2021-11-22 16:28:51 +00:00
Angel Pons 63c0fd2dbe mb/prodrive/hermes: Rename "internal audio" setting
The "internal audio connection" setting is actually about the front
panel audio. Rename functions and variables to reflect this.

Change-Id: I1be8f68ac3e8b91bc4983dc06daa37afb7bdf926
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin van Son <justin.van.son@prodrive-technologies.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-11-22 16:21:49 +00:00
Won Chung 667471b8d8 ec/google/chromeec: Add PLD to EC conn in ACPI table
Given EC CON and associated USB port objects, custom_pld or pld_group
information is retrieved from port and added to ACPI table as _PLD field
for typec connector.

BUG=b:202446737
TEST=emerge-brya coreboot & SSDT dump in Brya test device

Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: Ibc56ecd4e8954ffaace3acd9528a064b5fa2cf6f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-22 15:12:01 +00:00
Bernardo Perez Priego c47beec2d3 mb/intel/adlrvp: Use dedicated VBT files for ADL-M
ADL-M has its own set of VBT files to pick during execution,
this will avoid any conflict with other ADL variants.

VBT files added at chrome-internal:4138272

BUG=None
TEST= Boot device on LP5/LP4, corresponding VBT file should be loaded.

Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: Ibbf3f11c9277f5dcb3e12f9020f54ec843444c3f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58202
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Selma Bensaid <selma.bensaid@intel.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2021-11-22 15:11:36 +00:00
Michał Żygowski 708c937c11 arch/ppc64/include/arch/io.h: implement IO functions
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>

arch/ppc64/include/arch/io.h: use proper instructions for IO operations

Those instrunctions are:
* Load {byte,half,word} and Zero Caching Inhibited indeXed (l*zcix)
* Store {byte,half,word} Caching Inhibited indeXed (st*cix)
for in* and out*, respectively.

Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>

arch/ppc64/include/arch/io.h: implement istep reporting

Change-Id: Ib65c99888ba2e616893a55dff47d2b445052fa7c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57075
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-11-22 15:09:33 +00:00
Krystian Hebel 84f3807f5c drivers/uart: Let DRIVERS_UART_8250IO also depend on PPC64
There seems to be no operational differences between x86 and PPC64 for
UART 8250. Port number is the same. References:

* https://github.com/open-power/docs/issues/25
* https://github.com/3mdeb/openpower-coreboot-docs/blob/main/devnotes/porting.md#enabling-console

Tested on Talos II (https://raptorcs.com/TALOSII/). Works in QEMU as
well (actually in QEMU it works even without this change somehow).

Change-Id: Ib06001076b8eaa577a8d2159afea20afb610687d
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-11-22 15:02:50 +00:00
Marek Kasiewicz f1e401c6cb util/cbfstool/flashmap/fmap.c: fix fmaptool endianness bugs on BE
This patch makes all accesses to the FMAP fields explicitly little endian.
It fixes issue where build on BE host produced different binary image than
on LE.

Signed-off-by: Marek Kasiewicz <marek.kasiewicz@3mdeb.com>
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Change-Id: Ia88c0625cefa1e594ac1849271a71c3aacc8ce78
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55039
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-11-22 15:01:30 +00:00
Hsuan Ting Chen a5cbe27148 eventlog: Add a log type for Chrome OS diagnostics
Add events for Chrome OS diagnostics in eventlog tool:
* ELOG_TYPE_CROS_DIAGNOSTICS(0xb6): diagnostics-related events
* ELOG_CROS_LAUNCH_DIAGNOSTICS(0x01): sub-type for diagnostics boot

These events are not added anywhere currently. They will be added in
another separate commit.

Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org>
Change-Id: I1b67fdb46f64db33f581cfb5635103c9f5bbb302
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-22 14:59:37 +00:00
Arthur Heymans b2a442ed59 soc/intel/cannonlake: Fix PEG1 _PRT generation
Some weird things happen inside FSP and the routing is not correctly
applied, with PIN D being used but lacking a proper routing in ACPI.
To work around this issue generate _PRT for all 4 INT pins.

Change-Id: I5be6e4514f8c6a47bb887d9f9b95181c9f426a51
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58517
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-22 14:56:18 +00:00
Adam Liu 37e261f374 mainboard/google/brya: Enable dev screen in bios-stage for Brask
Add Kconfig item ENABLE_TCSS_DISPLAY_DETECTION.

TEST=Build with the VBT provided in issue b:199490251. Check the dev screen in bios-stage.
BUG=b:199490251, b:206014054

Signed-off-by: Adam Liu <adam.liu@quanta.corp-partner.google.com>
Change-Id: I5f34be030a6d819a0e93a2d479c4ff41bb14cfe2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-22 14:55:10 +00:00
David Wu 6de48981fa mb/google/brya: Move cr50 configuration to variant
Brya schematic will swap TPM I2C with touchscreen I2C,
so move into variant level.

BUG=b:195853169
TEST=build pass.

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ie5276527da135ec15045a81985ae006722871b0b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59472
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-22 14:54:44 +00:00
Malik_Hsu 797bc1b8e4 mb/google/brya/variants/primus: add fw_config_probe for ALC5682I-VS
Added fw_config_probe method to distinguish different audio codecs to
facilitate the use of different topology files by the OS.

BUG=b:205883511
TEST=emerge-brya coreboot chromeos-bootimage and check audio function

Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com>
Change-Id: I0d5b95e89154b2cb6b371f24cc1b151c23ff642f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-22 14:53:53 +00:00
Eric Lai 6b81adf8bc mb/google/brya/var/felwinter: Add ALC5682I-VS codec support
ALC5682I-VS will use in next build.

BUG=b:194367025
TEST=none.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I34d736fe1c39860443dac07435a21ccd0ee2f21c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-22 14:53:39 +00:00
Sean Rhodes 17441a3ac5 mainboard/starlabs: Add StarBook Mk V
Tested using MrChromeBox's `uefipayload_202107` branch:
* Windows 10
* Ubuntu 20.04
* MX Linux 19.4
* Manjaro 21

No known issues.

https://starlabs.systems/pages/starbook-specification

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I090971a9e8d2be5b08be886d00d304607304b645
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56088
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-22 14:53:04 +00:00
Seunghwan Kim be0722ac91 mb/google/dedede/var/bugzzy: Configure Acoustic noise mitigation UPDs
Enable Acoustic noise mitigation for bugzzy and set slew rate to 1/8
which is calibrated value for the board.

BUG=b:207046230
BRANCH=dedede
TEST=build firmware to UPD and Acoustic noise test

Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Change-Id: Id249a143efb9bce70f48fb466fed42e766a10937
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59480
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-11-22 14:47:50 +00:00
Sean Rhodes 69ed3ed5d8 soc/intel: Allow enable/disable ME via CMOS
Add .enable method that will set the CSME state. The state is based on
the new CMOS option me_state, with values of 0 and 1. The method is very
stable when switching between different firmware platforms.

This method should not be used in combination with USE_ME_CLEANER.

State 1 will result in:
ME: Current Working State   : 4
ME: Current Operation State : 1
ME: Current Operation Mode  : 3
ME: Error Code              : 2

State 0 will result in:
ME: Current Working State   : 5
ME: Current Operation State : 1
ME: Current Operation Mode  : 0
ME: Error Code              : 0

Tested on:
KBL-R: i7-8550u
CML: i3-10110u, i7-10710u
TGL: i3-1110G4, i7-1165G7

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I374db3b7c0ded71cdc18f27970252fec7220cc20
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-22 14:47:05 +00:00
Sean Rhodes 89b6d4bf12 3rdparty/blobs: Update submodule
This brings in EC firmware binaries for Star Labs laptops, as
well as a custom bootsplash image.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Iab5ff610b19fbe6a2e61999457a13a86d47f0ca7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-11-22 14:46:37 +00:00
Sean Rhodes 296994bec8 ec/starlabs: Add standardised ITE EC support
Add EC support that supports different Q Events and EC memory.
Created from the ITE IT5570E and IT8987E datasheets, all using
data port 0x4e.

Tested with Ubuntu 20.04.3 and Windows 10 on:

* StarBook Mk V (TGL + IT5570E):
*  ITE Firmware 1.00
*  Merlin Firmware 1.00

* LabTop Mk IV (CML + IT8987E):
*  ITE Firmware 1.04

* LabTop Mk III (KBL + IT8987E):
*  ITE Firmware 3.12

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I8023c26de23c874c84106fda96e64dcfa0c5ba32
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58343
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Andy Pont <andy.pont@sdcsystems.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-22 14:46:20 +00:00
Subrata Banik 6973a3e7c4 soc/intel/{adl,ehl,jsl,tgl}: Remove unused header `thermal.h`
This patch removes unused header inclusion as <intelblocks/thermal.h>
from several SoC finalize.c files.

Change-Id: Ic9ac0ffb352686af22cc9d11b61f904238eef278
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-11-22 08:02:48 +00:00
Subrata Banik b2e8bd8364 soc/intel/alderlake: Hook up common code for thermal configuration
Thermal configuration registers are now located behind PMC PWRMBASE
for Alder Lake Point PCH. Hence, ADL SoC to select
SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC to let thermal low threshold
is being set as per mainboard provided `pch_thermal_trip`.

Note: These thermal configuration registers are RW/O hence, setting
those early prior to FSP-S helps coreboot to set the desired low
thermal threshold for the platform.

BUG=b:193774296
TEST=Dump thermal configuration registers PWRMBASE+0x150c etc. prior
to FSP-S shows that registers are now programmed based on
'pch_thermal_trip' and lock register BIT31 is set.

Change-Id: I0f972f47845c123f4f74fd75091c9703d54db796
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59271
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-20 17:49:25 +00:00
Subrata Banik 8c45f236bc soc/intel/alderlake: Set `pch_thermal_trip` for Dynamic Thermal Shutdown
Set low maximum temp threshold value used for dynamic thermal sensor
shutdown consideration.

BUG=b:193774296

Change-Id: I7ee199c19a9d926a4135eeef3b3b481fbff74a79
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-11-20 17:49:11 +00:00
Subrata Banik 2ee30add35 soc/intel/common/thermal: Allow thermal configuration over PMC
Thermal configuration has evolved over PCH generations where
latest PCH has provided an option to allow thermal configuration
using PMC PWRMBASE registers.

This patch adds an option for impacted SoC to select the Kconfig
for allowing thermal configuration using PMC PCH MMIO space.

BUG=b:193774296
TEST=Able to build and boot hatch and adlrvp platform.

Change-Id: I0c6ae72610da39fc18ff252c440d006e83c570a0
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59209
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-20 17:49:00 +00:00
Sean Rhodes d7375b3fdd ec/starlabs: Remove old EC code
Remove old code in favour of new format of firmware API.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Iaf8f37a08c232b8754e57f022782f21284fa07dd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-11-20 11:53:48 +00:00
Subrata Banik 5a13d6617c soc/intel/common/thermal: Use `clrsetbits32()` for setting LTT
This patch uses `clrsetbits32` helper function to set thermal
device Low Temp Threshold (LTT) value.

BUG=b:193774296
TEST=Able to build and boot hatch and adlrvp with this change.

Change-Id: I51fea7bd2146ea29ef476218c006f7350b32c006
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59310
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-20 05:18:08 +00:00
Subrata Banik ca247629da soc/intel/common/thermal: Hook up IA thermal block to romstage
This patch ensures IA common thermal block is now able to compile
under romstage with necessary compilation issues fixed.

BUG=b:193774296

Change-Id: I3279f55436977ab9a47e04455d8469e50b5c33c8
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59391
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-20 05:17:56 +00:00
Subrata Banik c8193ce587 soc/intel/common/thermal: Drop unused parameter of pch_get_ltt_value()
`struct device *dev` as part of the pch_get_ltt_value() argument is
being used hence, replace with `void`.

BUG=b:193774296

Change-Id: Iecdf6f6c3023f896a27e212d7c59b2030a3fd116
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59390
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-20 05:17:46 +00:00
Bora Guvendik 31605959a5 soc/intel/alderlake: Update the VccIn Aux Imon IccMax for ADL-M
This patch updates the VccIn Aux Imon IccMax for ADL-M

Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I21753f2e5e9867f22c05e087cbf1f1e097d28bca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57325
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-19 22:52:26 +00:00
Joey Peng 7cbf203d9b mb/google/brya: Move EC_HOST_EVENT_USB_MUX wake event to S0ix only
If a USB_MUX_EVENT happens while the AP is in S3 during powerdown
transtion (S0->S3->S5), this will cause the device to boot again after
it has finished sequencing down to S5. Since S3 is not POR for ChromeOS
devices anymore, change this event to wake from S3 and S0ix to just
S0ix.

BUG=b:206867635
TEST=emerge-brya coreboot

Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: Icdab40b6a845a34246d7da336f43e970f7908301
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-19 22:51:56 +00:00
Patrick Georgi ef164196cb Documentation: Add some notes about how to integrate FSP
While we don't _want_ FSP, we can't get around it sometimes.  But when
using it, we can still try to establish best practices to make life
easier for everybody.

Change-Id: I4efd273e4141dc6dc4cf8bdebda9cffd0d7cc1a1
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2021-11-19 18:26:00 +00:00
Miriam Polzer 7dce190808 security/vboot: Add NVRAM counter for TPM 2.0
Create an NVRAM counter in TPM 2.0 that survives owner clear and can be
read and written without authorization. This counter allows to seal data
with the TPM that can only be unsealed before the counter was
incremented. It will be used during Chrome OS rollback to securely carry
data across a TPM clear.

Signed-off-by: Miriam Polzer <mpolzer@google.com>
Change-Id: I511dba3b3461713ce20fb2bda9fced0fee6517e1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-11-19 17:19:50 +00:00
Sheng-Liang Pan bef23d1f79 mb/google/volteer/var/chronicler: set DdrMemoryDown enable
as doc #632048, there is a fix in MRC for this sighting but DdrMemoryDown need to be set to 1.

BUG=b:192478111
BRANCH=volteer
TEST=FW_NAME=chronicler emerge-volteer coreboot chromeos-bootimage
Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: If7ead2d0bb2955a4f1b81d012ee2e2518b2a82e4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59373
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-19 15:35:25 +00:00
Angel Pons ada539ee50 util/inteltool/gpio.c: Correct register name
Document 319973-003 (ICH10 datasheet) and document 324645-006 (6-series
PCH datasheet) indicate that the name of this register is `GP_LVL3`,
not `GPIO_LVL3`. Correct the name.

Change-Id: I44cc41843c9f7cd0796bd198fb89447d787f155a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2021-11-19 15:10:20 +00:00
Varshit B Pandya f0e721050a mb/google/brya/var/redrix: Configure _DSC for CAM devices to ACPI_DEVICE_SLEEP_D3_COLD
Configure _DSC to ACPI_DEVICE_SLEEP_D3_COLD so that driver skips initial
probe during kernel boot and prevent privacy LED blink.

BUG=b:199823938
TEST=Build and boot redrix to OS. Verify entries in SSDT and monitor LED
during boot.

Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: I88ea1b87698c63e1bd69367ee857fba3f25c84ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59260
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-19 14:54:02 +00:00
Varshit B Pandya 04e8c2b5ff driver/intel/mipi_camera: Add support for _DSC field
The _DSC (Device State for Configuration) object evaluates to an integer
may be used to tell Linux the highest allowed D state for a device
during probe. The support for _DSC requires support from the kernel
bus type if the bus driver normally sets the device in D0 state for
probe.

The D states and thus also the allowed values for _DSC are listed below.
Number	State	Description
0	D0	Device fully powered on
1	D1
2	D2
3	D3hot
4	D3cold	Off

More details can be found here https://lkml.org/lkml/2021/10/25/397

BUG=none
BRANCH=none
TEST=Add corresponding field in brya, boot and dump SSDT to check if
_DSC field is as per expectation.

            Name (_ADR, Zero)  // _ADR: Address
            Name (_HID, "OVTI8856")  // _HID: Hardware ID
            Name (_UID, Zero)  // _UID: Unique ID
            Name (_DDN, "Ov 8856 Camera")  // _DDN: DOS Device Name
            Method (_STA, 0, NotSerialized)  // _STA: Status
            {
                Return (0x0F)
            }

            Method (_DSC, 0, NotSerialized)
            {
                Return (0x04)
            }

Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: I5471f144918413a2982f86beaf3dbf7e4e66cc9b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-19 14:53:06 +00:00
Patrick Georgi 423e9e0fc0 Documentation/lint: Use Super I/O instead of SuperIO
Change-Id: Idb16092b687ebffb319bc1908f08f350d612d36a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39451
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-11-19 14:47:20 +00:00
Angel Pons 65adc70165 util/inteltool: Add ICH10D PCI ID
Add the PCI device ID for the ICH10D southbridge. While we're at it,
also fix up whitespace in inteltool.h of an adjacent definition.

Change-Id: I98d88a9ce27d3ddaafd7123ee51b2111a8bef019
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2021-11-19 13:54:48 +00:00
Sean Rhodes c9bc7a7591 util/lint: Fix linters to work with coreboot-configurator
* Exclude .gif files from newline checking
* Exclude coreboot-configurator from checkpatch checking

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I1b07b7b05340409e5c1695cc7bbdea68f8190097
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
2021-11-19 13:34:55 +00:00
Meera Ravindranath 98e827ea74 mb/intel/adlrvp: Enable CPU PCIe RP 2
Disabling CPU PCIe RP 2 (commit:3fd39467b Fix S0ix regression)
causes regression in NVMe boot on ADL-P RVP boards.

Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I0b8b76a5537d8b80777cb7588ce6b22281af7882
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59392
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-19 06:21:21 +00:00
Sean Rhodes d58599dcb8 drivers/fsp: Rewrite post code hex values in lowercase
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I65a83fcd69296f13c63329701ba9ce53f7cc2cb3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-11-18 23:33:58 +00:00
Rob Barnes 188be6b270 mb/google/guybrush: Add variant_tpm_gpio_table
Add separate gpio table for TPM i2c and interrupt. Remove TPM gpios from
early_gpio_table. This allows for initializing TPM gpios separately from
other gpios.

BUG=b:200578885
BRANCH=None
TEST=Build and boot guybrush

Change-Id: I51d087087b166ec3bb3762bc1150b34db5b22f2f
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59083
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-18 23:33:15 +00:00
Eric Lai eae7bf2327 mb/google/brya/var/felwinter: Correct USB3 TCSS setting
Based on Intel Kit#615686, USB3 only needs to disable TBT and DMA per
port. And if uses USB3 directly you need to set TcssAuxOri accordingly.

BUG=b:206716691,b:205235144
TEST=USB function work as expected at USB3 only sku.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I303d042d6c80194ff48130fe4e9c04b49ca13ee8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-18 23:32:43 +00:00
Mark Hsieh 88295c35cc mb/google/brya/var/gimble: Include 2 new SPDs
Add SPD support to gimble for LPDDR4 memory part MT53E1G32D2NP-046 WT:B
and MT53E512M32D1NP-046 WT:B.

BUG=b:191574298
TEST=USE="project_gimble emerge-brya coreboot" and verify it builds
without error.

Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: Id3fc35605675b953bf993a29f35140f7721eedab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59299
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-18 23:32:22 +00:00
Wisley Chen da815303a3 mb/google/brya/var/redrix: De-assert SSD PERST# in romstage
After CB:57539 applied, it can support romstage GPIO table override.
We can move SSD PERST# de-assertion to romstage.

The reason for this is to give enough time after PERST#
deassertion so that the SSD has enough time to initialize before
the FSP scans the RPs for downstream devices.

BUG=b:199714453
TEST=build

Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: I242cb1517f564d9d135d523b1e7f95ac34d601f8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59269
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-18 23:31:58 +00:00